| In the 21st century, computer networks had grown rapidly in the world, affecting all aspects of human life. People enjoy the convenience of the computer networks, but also face many problems. The most prominent is the information security problem. In China, the research and practice of information security started later. Compared with developed countries, there is a large gap between them. So the information security problem is more prominent. Critical national infrastructures which are not likely to be introduced or used others' encryption technology can just only be researched and developed independently. In China, there are no decrypted chips so it is great significance to the information safety to produce independent intellectual property rights of the decrypted chips.This paper firstly introduces the cryptography knowledge, analyzes the advantages and disadvantages of the symmetric cryptosystem and asymmetric cryptosystem and determines the design scheme of decrypted chip using RSA and AES encryption algorithm. In the decrypted chip, RSA algorithm implements digital signatures and transfers the key of AES encryption algorithm and AES algorithm encrypts the large quantities of data. On this basis, it respectively presents the mathematical foundation, the structure and the different realization of the two encryption algorithms and compares and selects the facilitate FPGA realization. Analyzing the designs of S box in the AES algorithm, we determine to use Double Port RAM to implement S box. The amount of RAM is only 50.Secondly, the paper analyzes the construction principle, algebraic expressions, periods of iterative-output and property of affine transformation, points out the shortcomings of existing S box. Based on that, an improved S-box has been constructed. The method is affine transformation, the inverse element and affine transformation. The affine transformed pair must meet that periods of affine transformation matrix is 8 and the period periods of affine transformed pair is 16. The algebraic expression of S box has 255 items and period of iterative-output is 256 in the new S box.Thirdly, this article details the overall structure of the encryption chip and divides four parts according to the system function. There are control module, communication module, RSA encryption module and AES encryption module. The control module controls the coordination of data input/output module, RSA encryption module and AES encryption module; Communication module completes the acquisition, integration and distribution of input data, transmits the other modules requirements formatted data and outputs the produced data which can be recognized by the computer; RSA encryption module implements digital signatures and decrypts the key of AES encryption module; AES encryption module as the core part of the chip, mainly completes data encryption functions. Each module is implemented by Verilog VHDL language and processed the function simulation. Based on the XC5VLX110T chip which is a chip of the Virtex5 series, using the Xilinx 9.2I, the highest system frequency and the processing speed of the chip are respectively 249.522 MHz and 7.9847Gbps after Synthesize-XST.Finally, this paper simply introduces the cryptography and the key exchange technology and puts forward the exchanged keys solution using the digital signature algorithm. |
