Study On Train Communication Network Device Based On FPGA

ABSTRACT:In this paper, the Multifunction Vehicle Bus (MVB) controller chip is designed based on Field-programmable Gate Array (FPGA). There are three key parts as well as the most difficult ones as follows:the process of transfer signal crossing the clock domain, the synchronous process in the MVB communication and the Manchester decoding.Firstly, designing cross the clock domain based on FPGA will cause metastability. And the metastability can be reduced by transferring signal synchronously. Then, frame synchronization and bit synchronization in MVB communication are analyzed. According to train communication network standard, the frame synchronization module is designed that can identify error signal, further more, the quick bit synchronization module is designed to resist signal jitter based on DPLL and open-loop bit synchronization signal extraction. After that, the problems are analyzed such as data decoding in MVB communication. Finally, multipoint decoding algorithm based on active edges is raised with the better understanding of decoding algorithms and characters of MVB frame data coding,. In this way, frame data is decoded exactly.All above, the paper adopts the modularize method to do the program from top to bottom, designs with Verilog language, and uses Quartus II and ModelSim to synthesis and simulate. In the end, dose the board level debugging with EP1C3T100 Series chip of Altera Company, and gets clock signal and decoding signal of MVB frame input in oscillograph.