Design Of Data Storage And Transmission For Cone-beam CT 3D Roconstruction Based On FPGA

With advances in technology, CT technology has been increasingly widely used in the medical, industrial, aerospace and other fields. Being a new trend of CT technology development, cone-beam CT has been gradually replacing the traditional two-dimensional CT, with advantages of three-dimensional imaging, high spatial resolution, and high utilization percent of ray and quickly scanning, etc. But the algorithm of three-dimensional cone beam CT image reconstruction is more complex, which leads to the growing amount of data and calculation to be processed. So it needs greater storage capacity for memory bandwidth and higher data transmission speed and accuracy. As a result, it takes more and more time for the traditional single CPU to reconstruct images. Obviously, traditional single CPU can no longer achieve the speed of modern CT reconstruction. Hence, how to improve the speed of three-dimensional cone-beam CT reconstruction is becoming a hot research field.FPGA is a programmable gate array and is popular for its programmable property in the filed of digital system design. In this paper, firstly, based on scientific and technical literature at home and abroad, secondly, to get memory bandwidth and high data transmission speed that the algorithm in the process of three-dimensional cone-beam CT reconstruction requires, thirdly, after analyzing the parallel specificity of the current main algorithm FDK and considering the parallel processing structure of FPGA, it is presented an implementation for small scale CT reconstruction system, of which data storage section's and transmission section's hardware and software designs have been completed.As to Hardware design, the storage section has two options, one is to use SDR as main memory, the other is to use DDR as main memory, and both of them use SRAM as off-chip cache. The hardware parts of Storage need to be designed mainly includes FPGA peripheral circuits, the external circuits of memory chip, the circuits to connect the two parts and power circuit, etc. Each chip's selection is based on its technical indicators for miniature image reconstruction system. For instance, CY7C68013A is chosen to be USB interface's control chip for transmission part. While designing the circuits, it should be paid attention to its external crystal oscillator circuit, and the connecting circuits between the external program memory and the FPGA. Every design section is provided with circuit schematic diagrams in the paper.For Software design, the storage part has realized the SDR, DDR memory controller and the SRAM control logic in internal FPGA; transmission part has completed designs for the interface logic between USB and FPGA, USB firmware, device driver to connect to host computer, and application program for host computer, etc.After completing the hardware and software designs, both the memory system and the transfer system were timing simulated and speed tested. The consequences proved that the system could come up to the design expectation with good properties. It can also continue to complete its implementation section of CT reconstruction algorithm.At the end of the paper, it summarized the design of the system, pointed out the deficiencies and defects, and prospected the development that cone-beam CT three-dimensional reconstruction will achieve by using of FPGA.