The Vector Integer Unit Design And Implementation Based On PowerPC Architecture

This thesis mainly focuses on the research of the architecture of the vector arithmetic unit, and finishes the confirmation of architecture and the architecture design of the vector integer unit. The design and the verification of key circuit modules of the vector simple fixed point unit and the vector complicated fixed point unit are given.The vector integer unit, designed in this thesis, is the expansion unit of the X CPU arithmetic unit. It mainly takes in charge of the processing of the wide data. Based on the sufficient understanding of the architecture of PowerPC, this article finishes the full custom design of the vector integer unit. It is finished that the design of the four dynamic logical modules and the clock circuit of the dynamic modules in the vector simple fixed point unit. The design of the Booth modules, partial product circuit and the full adder modules in the vector complicated fixed point unit is also accomplished. Based on the comparison of many kinds of full adders through simulation, the CLSA adder is adopted instead of the CLA adder at last. All the modules are verified by the tools such as Hspice, Verilog-XL, NC-Verilog. The timing analysis and power testing of key modules and circuits are done under the Hspice software environment. The chip is accomplished based on 0.13μm CMOS process. After the layout design, the back-end simulation is finished under the NanoSim. The thesis finishes the custom design on the Vector integer unit in the X CPU. The function simulation and design optimization are made in this article. The results show that the design in this article meets the stated requests very well.