The Design Of The First Level Cache Based On PowerPC Architecture

This work focuses on the design of the first-level Cache based on PowerPC architecture . In order to achieve good performance, the first-level cache is split physically into two parts, one for instruction and the other for data, then we begin by briefly describing the method of the cache module. In order to match up with the CPU speed, the mapping strategy is finally decided to choose set-associative, and used the physical addressing, the plru replacement policy is selected to improve the hit rate. We used three methods to reduce the wait time of the CPU, they are self-time technique, hardware prefetching technology, non blocking technology. Some new technologys are used in this paper, such as, the self-time control circuit, which is used as a switch to control the word-line. it can automatic tracking the delay of bit-line and effectively eliminate the affect of operating environment and foundry technology, the time of the process of turnoff the word-line is only 0.26ns. Multistage method is adopted to decrease the input Series resistance of the gate and the delay in the Decoding circuit, in order to improve the read speed, latch type is adopted when we design the sensitive amplifier, and the read speed of the sensitive amplifier is improved by 0.23ns. Finally, NC-verilog is used to simulate the function of the cache, and the result is totally satisfy the requirement.