A Fixed Outline Floorplanning Algorithm Forre Lfapxegda M Dateesriiganl

Recently, FPGA is the key device for various embedded systems, communicationand computing. According to improving of FPGA technology, FPGA is used for the realcommercial systems instead of ASIC. FPGA design has some special properties. Forexample, the delay of LUT (Look Up Table) is the same for all logic function undersome number of fanins. The routing fabrics have routing area and a switch box whichhas a relatively large delay value when the routing should be cranked.There are various the conventional approaches for the speed optimization forFPGA design. The conventional approaches proposed simulated annealing basedplacement such as the famous VPR tool.IARFP (Insertion After Remove Floorplanning) is an effective FOFP method andhas better results compared with similar methods. In this research, the novel FPGAdesign method for the high speed is proposed based on IARFP. The proposed methodhas two parts, placement with delay optimization and logic refinement by using FPGAfeatures. The placement method can minimize the long delay path by module swapping.The logic refinement method can also improve the logic delay.The edges in the network are all assigned an initial weight. The edge weights onthe critical paths all increase after one iteration. The cost function of the floorplanalgorithm considers the edge weights when computing the critical paths. And it alsoconsiders the FPGA properties and it can handle multiple optimization targets. Based onthe FPGA properties, after floorplanning, choose one or more modules on the criticalpath and duplicate it. This operation may decrease the length of the critical path undersome condition. Map some blocks into one block may save logic resource and at thesame time decrease logic delay.Experimental results show that an average of 13.47% improvement is achieved bydelay optimization method and an average of 8.16% improvement is achieved by thelogic refinement method.