| With feature-sizes below 0.25μm, interconnect delays account for over 40% of worst delays [56]. Transitions to 0.18μ m and 0.13μm further increase this figure, and thus the relative importance of timing-driven placement for VLSI. We introduce a novel minimization of maximal path delay that extends previously known algorithms for delay budgeting. The proposed placement algorithms have provable properties and are fast in practice.; These algorithms have been implemented within the framework of a scalable min-cut placer with proven empirical record wirelength- and congestion-driven placement [21]. We show that our placer is able to improve upon worst-path signal delay with only a modest wirelength penalty. |
