Research And Design Of Frequency Hopping Synthesizer Basedon DDS

Now there is a problem that the existing frequency-hopping signal generator can not meet the new military hopping radio, proposing a new design method of signal generator - Information Split Parallel Transmission Method, and this method can improve the frequency resolution and hopping speed advantage. Information split parallel transmission method is that after a piece of information following certain rules is splited to more than one message and sent them at the same time. According to the specific needs of the situation,using this new method the signal generator can increase parallel lines into large ones in order to further improve the performance of, can also cut parallel lines to reduce the system complexity. Under actual conditions of use, signal generator need to compromise according to the performance and complexity, and this paper for its own needs adopts a 3-way parallel transmission, making frequency hopping speed to increase one times and the frequency resolution to improve 2 times. In addition to the program there are three obvious advantages: onely, the signal split can be encrypted respectively, and can not easily be the enemy to obtain all the information, enhancing the signal confidentiality; secondly, multi-channel parallel transmission can shorten information transmission time, reducing the chance of enemy interference detection and ensure the effective transmission of information; finally, while producing confusion signals, the enemy can not know which one is the useful signal, which is the unwanted signal, and i Increasing the confusion of the radio.The system mainly consists of PLL circuit, DDS circuit, processor circuit and other components. In this paper, the Cyclone II family FPGA chip is the control module instead of the traditional common MCU with Nios II system implemented in an embedded microchip. A number of peripheral circuit modules, including a string and converted circuit and two auxiliary DDS chips are integrated into the FPGA internally. After the integration performance improved, reliability increased, circuit size and lower cost reduced, and the system can achieve soft-upgrade.