Research And Implementation On Real-time Speaker Recognition Algorithmin In Multiplexing Parallel Model

As communication technology highly evolving, telephone communication becomes the main platform of association and information exchange between people, Multiplexing parallel Speaker Recognition which is based on telephone communication turn into extensive research assignment. At present many Speaker Recognition Systems is based on the computer software or DSP chip, which has flexible system implementation, but with regards to telephone communication it is worse in real time.The FPGA(Field-Programmable Gate Array) chip has advantage of high clock frequency, small inner part postpone,all control logic completed by hardware,it is quicky speed,high efficiency,and suitable for the large data stream of highly transmission control. There is two characteristics of DSP+FPGA structure,first structure flexible, strong general use,and the suitable for modularization design,thus it can raise calculate efficiency and be applicable to actually processing system;secondly, it has short development period and the system is easy to maintain and upgrade.This paper's main work includes:(1) Aiming at characteristic of Multiplexing parallel Speaker Recognition,data throughput,resource requirement and calculate speed,this paper puts forward the system based on DSP and FPGA.(2) According to the characteristics of Multiplexing parallel Speaker Recognition,researching on the characteristic parameter and matching model,this paper designs recognition algorithm based on Mel Frequency Cepstrum Coefficient(MFCC) and Vector Quantization (VQ).(3) According to speaker mode matching method,aiming at the requirement identification rate and processing speed in system,this paper introduces code vector separability improved VQ algorithm,which advances the recognition performance;and in order to improving matching speed,add equal-average nearnest neighbor search(ENNS) to improved VQ algorithm. Simulation shows that: recognition performance and matching speed get major increase.(4) Then, this paper completes the related design of DSP , include designing data interface,HPI(DSP and host communication),EMIF(DSP and FPGA communication),and DSP related register set;Design and optimizing improved VQ algorithm based on TI 6455;make the experiment about relative error the DSP fixed-point and VC float-point result,and matching time.(5) The experiment shows that: the system can process multiplexing parallel telephone speech,and recognition performance is well.