The FPGA Implementation Of 2-D Discrete Wavelet Transform

Wavelet transform is a very important production in the phylogeny of mathematics. Though wavelet transform is a new theory, it has strongly impacted on both mathmatics and engineering applications. The discrete wavelet transform (DWT) has been used as the core transforming technology in JPEG2000, a newest static image compression standard.Firstly, this thesis analyzes the theory fundamental of wavelet transform in details, and also introduces multi-resolution analysis (MRA), Mallat algorithm and Lifting Scheme. Then both the wavelet filters adopted in JPEG2000 and a new filter LS97 are introduced. The LS97 wavelet characterizes simple coefficients, being easy to implement with hardware and good compatibility with the CDF97 wavelet, so it can be used as a substitute for CDF97. A Matlab simulation is performed to test the compatibility between CDF97 and LS97, and the results show they almost have same performance. After selecting wavelet filters, this thesis designs the architecture of 2-D DWT. In the course of design, some approaches are applied to the normal 2-D DWT for optimizing the architecture, such as combination of scale step in DWT for rows and for columns which can reduce the number of multiplication by 2 times, substituting shift-add for multiplication and extracting common operator in the shift-add, etc. The embedded symmetric extension technology is used for the calculation of data in the boundary, so the architecture need not the additonal RAMs for data extension. To improve the percentage of hardware utilizing, this thesis combines the Le Gall 53 wavelet with the LS97 wavelet, and just one signal can control the switch of two DWT filters. In order to reduce the size of inner RAMs, a line-based approach for the implementation of the wavelet transform is used, so the architecture can complete DWT for the whole image using only 6 rows of inner RAMs. The frequency of the design is largely improved by using pipeline technology. At last, the architecture of inverse DWT is also proposed.On the basis of the architecture, the thesis describes the whole design in Verilog HDL at the full synthesizable RTL level with synchronous design technology. The simulation and implementation of forward and inverse DWT are performed on Xilinx's ISE6.3i, and the results show that the design can quickly and precisely complete forward and inverse DWT with reversible (Le Gall 53) and irreversible (LS97) filters, and can meet the real-time requirements for all kinds of application.