Font Size: a A A

Research And Implementation Of JPEG2000 5/3 Lifting Based Wavelet On FPGA

Posted on:2008-05-06Degree:MasterType:Thesis
Country:ChinaCandidate:W B DaiFull Text:PDF
GTID:2178360215474465Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
The custom JPEG compress standard is based on DCT, so the blocking effect is significant under high compress rate. The new standard JPEG2000 changed obviously, for it is based on DWT. JPEG2000 supports lossless and lossy compression of continuous tone and bilevel images with superior low bit-rate distortion and subjective performance; it also supports ROI and progressive transmission. It is necessary to process real time and lossless compression on image sometimes, but it is expensive to achieve the goal by using generic CPU and software, or even it is impossible. For hardware solution is faster than software solution, it is a good choice to implement JPEG2000 compression with hardware, such as FPGA.This thesis focus on hardware implementation of wavelet transform which is the core of JPEG2000, and presents a folding architecture based on sharing predicting circuit and updating circuit. The architecture takes advantages of lifting based 5/3 wavelet transform fully, so the register performance is high. It has such features: employed line based input circuit to fit the output of front circuit and reduce the cache numbers; improved hardware using rate to 100% by sharing the predicting circuit and updating circuit; employed embedded extension as boundary extension to avoid the pre-processing circuit; inserted pipeline registers into critical path to improve the top working frequency of circuit; employed shifters instead of multipliers to save hardware resource.We implemented the architecture by HDL, and synthesized it in EDA tools. We also did a simulation on the result of synthesis, the simulation showed that the design is right and the performance is high. When the target device is Altera's Cyclone, 1D wavelet transform consumed 214 LEs, the top frequency is 153MHz.This thesis also presents a 2D wavelet transform architecture based on the 1D wavelet transform architecture, which processes row and array data simultaneously by a ping-pong cache.
Keywords/Search Tags:Lifting Scheme, DWT, FPGA, JPEG2000
PDF Full Text Request
Related items