The Theory Of Synchronization Applied In The Increment Of E1 Link

With the development of communication technology, the communication will become digital, synthetical, intelligentized, personal and global step by step. And the access network is the key of the modernization of the communication. The introduction of the V5 standard interface in exchange realizes the digital link between the local exchange and access network, makes the digital channel connect with the subscribers directly or more closely, and finally achieves the digital access network. In the course of the data transmission in the access network, the access network must achieve synchronization in order to transmit datum accurately.Associated with the research project, the author has done some research on the technology of synchronization in the development of the QE1 (E1X4) transceiver, which is one type of the transceiver of Hitron's access network equipment HTC-5200AN. The paper describes the development of the technology of synchronization, and then introduces the basic Hitron's access network equipment HTC-5200AN, including the basic knowledge and network model. After analyzing the effect of El transceiver in the HTC-5200AN and the access network, the paper explains the purpose of QE1 (E1 4) and the software and hardware design scheme. With the current condition, the paper raises the point of synchronization in the QE1's development, including the synchronization of bit, frame, multiframe and network and analyses the performance frame synchronization system based on the theory of probability and finally explains the realization of the technology of synchronization.The hardware circuit diagram of QE1 and some software flow chart have been offered in the paper. QE1 achieve the whole synchronization by software and hardware. During the course of the initialization of the QE1 system, the chip PM4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. After PM4354 accomplishes the bitsynchronization, QEl will read the status registers of the PM4354 to get the status of each El circuit and choose recovered clock of the specified the El circuit as the external timing source of the whole HTC-5200AN equipment. Thereby, the choice of external timing source brought by the changing from the El to QEl has been resolved. In the related chapters, the paper will explain the arithmetic of synchronization of bit, frame and multiframe in the PM4354 hardware and describe the software arithmetic and hardware sketch map of net synchronization.