The Development Of The PCI Bus Based High-Speed Data Communication System Between Two Personal Computres

In some real-time systems which have mass of calculation to do and need to show the calculated results, the tasks of calculation and display are shared by two PCs in order to meet the demand for calculation speed. Through high-speed data transmission, the calculated results and control command are transferred between the two PCs. The system made according to the architecture isn't expensive and can be easily realized. The key question is how to realize high-speed data intercommunication between the two PCs.The high-speed data communication based on PCI bus between the two PCs is discussed in two aspects(hardware and software) in the paper. Firstly, PCI bus specification is introduced in the paper. Approach to implement PCI interface is discussed. FIFO data channel of PCI interface chip S5933 and approach of realizing PCI Bus Master DMA through the FIFO is introduced in detail. The reason for choosing S5933's FIFO to transfer data at high speed is clarified. Secondly, the design process of hardware is introduced. Hardware block diagram of the PC high-speed data communication system is given. Two CPLDs(Complex Programmable Logic Device) are adopted to design the logic of controlling data transmission. The process of data transmission are controlled by several foundation modules. Schematics of all foundation modules and Verilog source program are given. Finally, The design process of device driver and application are introduced. The main code of device driver, developed using WinDriver toolkit and with the DLL encapsulation, is given. Besides, practical measurement are made for whole design, and various factors of affecting PCI bus's the speed of data transmission are analyzed in detail on the base of measurement result.Design of Logic control circuits, device driver and application of the high-speed data communication system based on PCI bus are completed. With S5933 bus master (DMA), Bidirectional and high-speed data transmission are realized. The test results show that all demands of the design are achieved in speed of data transmission and system's function.