Research And Implementation Of High-Speed Digital Multiplexer

This subject is a part of "Imaging Inspection for Ground System ", which receives 88 channels image data of 10bit/10MHz from CCD, save and display it at the same time. This subject is the pre-processing part of the whole system, it receives image data from CCD and multiplexes four tributary signals into one channel signal that is image data of 10bit/40MHzoBut in most applications, the implementation of digital multiplexer adopt multiplexing based on bit primarily by Application Specific Intergrated Circuit (ASIC) or analog circuit on specified orders. Although in recent years, Programmable Logic Device(PLD)has been used in digital multiplexing, they are limited to multiplexing based on bit and multiplexing based on byte. These methods are easily implemented and required simple equipment, but they destroy frame structure and require to insert some synchronous code?In addition, these method can't utilize synchronous signal of Camera Link Interface Standard effectively. After careful research of current multiplex methods, the paper adopts and improve multiplexing based on frame and implement it by CPLD. The method ultize synchronous signal of Camera Link effectively and needn't insert synchronous code in multiplexed signal.Thus, the followed processing DSP unit can implement demultiplexing easily even without given demultiplexer. In addition, the method can strongly correct some error caused by delaying on input . It is a good robustness system.