Soft IP Core Design Of Parallel Process And Motion Estimate Section Of Video DSP

This paper is based on the prepare project of National 863 high technology project (863-SOC-Y-2-16). This paper studies the IP core design and hardware realization of Video Digital Signal Processor XY-VDSP.First, the outline of video compress principle and normal processor structure are introduced in this paper. Then, we present the system scheme of instruction and hardware structure. And parallel processor array construction, parallel processor data path design, parallel processor register bank design and motion estimation coprocessor design are described in detail in this paper.hi the project, author's work emphasizes on the parallel process section design and motion estimation design.XY-VDSP is designed with Verilog Hardware Description Language. We use Altera FPGA APEX20KE1000E to implement our design. The FPGA design and hardware test of the design is presented in the end of this paper.