Programmable Digital Pipeline Delay Module At Trigger System In Beijing Spectrometer

Beijing Spectrometer (BESIII), the National major Project at the Institute of High Energy Physics is approved and now the relative R&D and preliminary Designing are undergoing. The trigger system of BESIII is one of the most important parts of the real-time data acquisition (DAQ) system of BESIII, which must be studied and tested carefully before the final design. Moreover, regulating the signals from the sub-detectors of BESIII is the key technique that could determinates whether trigger system discriminates the good events.This paper describes a Pipelined Digital Programmable delay module, which is to be used in the Global Trigger, designed as a single width 6U standard VME module. Two main method are used in the preliminary design: One utilizes Shit Register and Multiplexers, which is simple and reliable. The other one makes use of the advantages of individual Read and Write bus of a Dual port RAM. The input signal is written to WRITE port. By changing of the difference of write address and read address, a delayed signal from READ port is achieved. The two methods have different idea but reach the same goal and have the properties that are pure digital delay, little error, compendious circuit and maneuverability. This module works with a clock of 40MHz and its input accept LVDS signal, output are both in LVDS and ECL standard. Thesetting of the delay parameters is realized with VME software commands. The content of FPGA is downloadable via PROM, JTAG or the special port on chip by XILINX software.The module can delay input signals from 0ns to 1.8us stepping by 25ns. It's precision is 25ns. The module has been tested and satisfactory in BESâ…¢.