The Development Of The VME Crate Fast Controlling Module For The Global Trigger System In BESⅢ

Beijing Spectrometer (BESIII), the National major Project at the Institute of High Energy Physics is approved and now the relative R&D and preliminary Designing are undergoing. As one of the most important parts of the real-time data acquisition (DAQ) system of BESIII, the Trigger System of BESIII , where many new technology will be used ,must be studied and tested carefully before the final design. VME Bus system has high performance of stability and throughput, which is widely used in many electronics systems of High Energy Spectrometer. The Trigger System of BESIII is just based on VME Bus system. At the same time, using the Field Programmable Gate Array—FPGA can simplify the design and shorten the long time needed for PCB design and fabrication, by taking advantage of its flexibility and programmability.Based upon both the VME Bus technology and the FPGA technology , the VME Crate Fast Controlling Module, which will be used in the Global Trigger sysytem , has been designed in this paper. As a part of the the whole circuit of the trigger timing and control logic ( TTC) .which is the heart of the trigger system , this module takes an important part in the design of TTC.The CFCTL Module is able to drive the Fast Controlling signal LI, CHK, RESET upto the User-Defined VME Bus in order to control the read-out of the data from the VME Crate, and gather the read-out state signals RERR,FULL,EMPT from the VME Crate upto the Main Trigger System of the Trigger System, and fan-out clock signals to sub-systems in the Trigger System.In another word, the CFCTL Module is able to count the number of input signals L1,RERR, and send interrupt requests under the control of the programs upto VME bus interrupt handler when the counts equal to the preset counts, then at the right time the interrupt service routine notifys the the real-time data acquisition (DAQ) system of BESIII to begin read the data, or notifys the Main Trigger System of the Trigger System to deal with the situation in the case of RERR or FULL being valid .In addition , the CFCTL Module is able to shift the phase of the input clock by unit of 90 degrees, and fan-out 16 channels of clock signals to sub-systems in the Trigger System.By means of both "the counting logic able to preset the thresholds of the counters" and "the logic for bidirectional counters with the control of pause" brought forward by the author , this paper has solved the puzzle that the frequence at which the VME bus master module can deal with the interruipts doesn't match that of input signal, and avoid themetastability caused by asynchronization between the system clock and some signals, consequently realize the design demand of the CFCTL module.The chief function of the CFCTL module produced by the author, which is a single width 6U standard VME module, a 4-layer PCB, has been realized mainly by means of a chip of FPGA which type is XC2S50-5-PQ208C. The computer simulation result for the chip of the FPGA on the CFCTL module and the test result for the CFCTL module PCB have indicated that the design of the CFCTL module accords with the timing standard of the VME Bus and the demand from the the Trigger System of BESIII.