FastHLS:A New High-Level Synthesis Framework For Software-Defined Hardware

Today,the upgrading of the information industry has put forward new requirements for rapid chip design.The EDA field is particularly important,and it is also one of the industrial software fields that the country considers to be stuck.High-level synthesis(HLS)tools in EDA are sought after as a new generation of chip front-end design tools,which can help software developers to quickly design hardware circuits through high-level languages.It is believed that the direction of software-defined hardware(SDH)is an important development trend of future EDA tool intelligence.This research has made major work and contributions in the core framework,key algorithms,and tool design for the high-level synthesis method of software-defined hardware.1)A new high-level synthesis method framework for software-defined hardware-FastHLS is proposed,and the complete processing process and tool chain from binary instruction code to structure,structure to system-level circuit step-by-step construction are designed.The core idea of the whole processing process is to transform the high-level synthesis problem into the problem of structure and construction of binary instruction code translation through dimensionality reduction,and to find isomorphisms structure that meet the requirements of resource and performance constraints in the dimension of structure by designing new algorithms.After constructing this structure,it is transformed into various hardware architectures(for example: dedicated logic circuits,RISC processors,VLIW architecture processor structure,etc.),and finally mapped to an abstract HAC hardware structure to complete the software-defined hardware.The design realizes the highlevel synthesis work at the SoC level without relying on the high-level language compiler,and effectively separates the coupling relationship between software development and hardware automation design.2)The implementation details of FastHLS core algorithm and key technologies are proposed,including structure optimization method,architecture generation method,special structure translation,debugging strategy and mechanism,dynamic redundancy elimination method,etc.In order to realize the construction of the circuit,a H＿rtl(I＿b,ω)operator is designed,and the implementation method and process are given,and the structure construction from the instruction level to the module level is completed by iterating the instruction template repeatedly;In order to further make the isomorphic structure meet the performance and resource requirements,two structural optimization algorithms are designed: one is the MinR-PI optimization algorithm that improves the performance as much as possible under the constraint of minimum resource construction;The other is the BalR-PI optimization algorithm which is resource-constrained under the premise of parallelism and performance priority for full translation with priority structure.These two algorithms can provide developers with more hardware structure solutions;In order to make the high-level synthesis tools achieve better compatible software development and code reusability,the RCB-Detect static analysis algorithm is designed to detect repeated instruction sequences in the code,and the combination scheme and module reference suggestions of reusable modules are given.In order to solve the related problems of special structure,redundancy elimination and code debugging,the translation of some special instruction structures is designed,such as interrupt processing,memory access,etc.more hardware resources.3)Completed the development and evaluation of FastHLS tools,and conducted experimental tests on the entire tool chain.In the experimental test results,it is found that it has achieved better results than similar tools in terms of compilation speed,synthesibility,and chip resource usage.Ultimately,this research has made breakthroughs in high-level synthesis in reusability,reliability,ease of use,and applicability.