Co-Design And Optimization Of Software And Hardware For The NoC-Based Neuromorphic Processor

As we all know,the brain has great advantages in information processing,and can simultaneously perform many complex tasks such as recognition,reasoning,and learning with only about 20W power.In recent years,artificial intelligence(AI),represented by deep learning,has made breakthroughs by simply learning from the hierarchical structure and learning and training characteristics of the brain system.However,there is still a big gap between AI and neuromorphic intelligence.In order to reduce the gap,neuromorphic computing provides a new way,which is to simultaneously imitate the brain system from both the neural network algorithm and the hardware architecture.The former imitates the spatio-tempral correlation of the brain to construct the spiking neural network(SNN)that uses pulses as the form of transmission;The latter imitates the hierarchical structure and information processing mechanism of the brain to construct a neuromorphic processor based on the distributed parallel and integrated memory/computation many-core system.With the increase in the complexity of SNN and its application range,neuromorphic processors can hardly meet its massive,concurrent,and complex spike data interaction requirements.This will disturb the spatio-tempral correlation in SNN,and will reduce the accuracy of SNN,and have an impact on the real-time feature of the hardware system.How to design a high-performance,real-time and parallel system for SNN applications has become a key research area in the industry and academia.In this paper,We dedicated to research the co-design and optimization of software and hardware for the NoC-based neuromorphic processor.Given the communication characteristics of different SNN structures and applications under various hardware structures,we design and optimize the Network-on-Chip(NoC)communication system in the neuromorphic processor.We explored the optimization work of software and hardware co-design in neuromorphic computing,such as the communication efficiency between the neuromorphic cores in the NoC-based neuromorphic processor,the optimization of the NoC architecture,and the optimization of the SNN structure.By designing an efficient SNN mapping algorithm and a SNN/NoC software and hardware co-design framework,we fully explore internal parallelism in the SNN/NoC structure and maximize communication efficiency,and finally get a NoC system that optimizes the design goals of software and hardware.At the same time,in order to fully consider the real-time feature of SNN on the NoC-based neuromorphic process and accelerate the co-design space exploration,we design a performance evaluation model that can conduct theoretical analysis of the communication and computation process in the neuromorphic processor.Our contributions are as follows:·We propose a SNN mapping toolchain called SNEAP.The toolchain optimizes the partitioning of spike communication tasks and the mapping of communication resources by analyzing the communication behavior of SNN on the NoC-based neuromorphic processor.The two components of division and mapping in SNEAP will optimize the on-chip communication efficiency from the inter-core spike communication volume and communication distance.For the partitioning component,we use a multi-level graph partitioning algorithm to quickly divide SNN into multiple neuron clusters under hardware resource constraints and optimize the inter-core spike communication volume;For the mapping component,we use a heuristic algorithm to map the clusters to the neuromorphic cores and optimize the delay and energy consumption of the entire processor.Meanwhile,we have greatly reduced the end-to-end execution time of the mapping component by replacing the optimization target from the results generated by the simulator with the communication distance that can be directly calculated.·We propose a LSM/NoC co-design search framework for the NoC-based neuromorphic processor.The framework uses a heuristic search algorithm to explore the LSM/NoC co-design space,so as to automatically find the multi-objective optimal LSM/NoC design scheme.The framework overcomes the search difficulty caused by the highdimensional and complex LSM/NoC co-design space by using the heuristic algorithm to automatically search such spaces quickly.Meanwhile,the gap between software and hardware design has been reduced,and results of LSM/NoC design pair have a good performance in the design goals of software and hardware.·We propose a communication performance model based on the recursive calculation method to evaluate the upper-bound latency for each spike data stream in SNN.Before the SNN with real-time requirements is deployed on the NoC-based neuromorphic processor,it must ensure that the upper-bound latency of each spike data stream in the worst case does not violate its limit of real-time.So we conduct a theoretical analysis of the communication behavior of each spike data stream to obtain the upper-bound latency of each data stream in the worst case.Our model can support two buffer structures of NoC,namely single FIFO structure and virtual channel structure.The experimental results show that the error of upper-bound latency estimated by our model and simulator is within 15%,and our model can give tighter upper-bound latency than other models.·We propose a performance evaluation framework based on the infrastructure of neuromorphic processor.The framework consists of a hardware design instance constructor and a performance model.The hardware design instance constructor generates a hardware design instance based on the infrastructure of neuromorphic processor and the SNN/hardware structural parameters.The performance model quickly evaluates the latency,power and area of the computing part of the neuromorphic processor by combining the SNN/hardware structural parameters with the evaluation results of each hardware units.The performance evaluation model is an early design space exploration tool,which can perform rapid high-dimensional design space exploration within a wide range of architecture/microarchitecture parameters.The model has accurate modeling results,with the average power and area errors below 8%when validated against IBM’s TrueNorth.In addition,we use our model to explore the design space of the Liquid State Machine.The experimental results show that by choosing the efficiency-optimized design,we can obtain a 2.94x improvement in cost efficiency with less than 1%sacrifice on latency over latency-optimized design.