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Research On Neuromorphic Computing Circuits And Systems With Memristive Devices

Posted on:2023-05-19Degree:DoctorType:Dissertation
Country:ChinaCandidate:J K LuFull Text:PDF
GTID:1528306902464134Subject:Electronic Science and Technology
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With the advancement of the fourth information revolution,applications such as big data,Internet of Things,and artificial intelligence are rapidly emerging.How to efficiently store,communicate and process the massive generated data has become one of the major challenges in the current electronic information field.Von Neumann architecture refers to a computing architecture that separates data storage and processing.Currently,it is limited by the performance mismatch between memory and processors,which has become a bottleneck limiting processor performance and efficiency.At the same time,Moore’s Law is gradually failing,and the technology path that relies on device size scaling to improve chip performance appears power consumption and reliability problems,further exacerbating the deterioration of the von Neumann bottleneck.Therefore,it is urgent to seek breakthroughs from the device,circuit,algorithm and architecture levels.Neuromorphic computing,which draws on the organizational structure and computing paradigm of the human brain,has attracted widespread international attention for its strong computing power and efficiency.The memristor has the characteristics of continuously adjustable resistance value,which is very suitable for simulating synaptic device in neuromorphic.Besides,the memristor has both storage and computing functions,realizing processing with memory from the device level.Therefore,it is considered as ideal hardware unit for realizing low-power and high-density neuromorphic computing platforms.However,the current neuromorphic computing based on memristor synapses is still in the initial stage of research,and there are still many problems and challenges.In this paper,the synaptic properties of memristive devices,the realization of in-situ learning functions and the large-scale neuromorphic system integration scheme are studied,and the following innovative results are achieved:(1)The research on spiking neural network based on ion-transistor synaptic devices.First,we propose a 1T1E synaptic cell structure for modeling heterosynaptic plasticity and validate the STDP and anti-STDP properties of 1T1E synapses.After that,a supervised learning spiking neural network system was constructed based on the 1T1E synapse,and experiments proved the in-situ learning ability of the network.We combine the proposed supervised learning network with neuromorphic sensors and apply it to spatiotemporal-coding information processing task.Finally,the experimental analysis shows that the 1T1E synapse with excellent synaptic properties is an ideal synaptic device for constructing in-situ learning SNN.(2)The study on neuromorphic in-situ learning computing core based on RRAM synaptic array.The synapse part adopts the 2T2R analog weight synapse with a scale of 256×64,combined with the peripheral read-write circuit and multiplexed digital neurons,to realize the synaptic computing function.The synaptic weights can be adjusted in real time through the configurable RRAM write circuit to realize the memory and recognition functions of precise time spike train.We then demonstrate the function of the network on a phase-coded image recognition task.Finally,the experiment based on RRAM array test board verifies the in-situ learning ability of the network.The above experimental results provide a feasible method for the development of neuromorphic technologies with adaptive functions.(3)The study on a multi-core adaptive SNN architecture based on RRAM synaptic array.In terms of hardware design,the ternary weight 4T2R synaptic structure,hardware-friendly multiplexed digital integrate-and-firing neurons and temporal-coding learning circuits are used.The device,circuit,algorithm and circuit are co-designed to reduce the negatic effect of device non-ideal characteristics and improve the efficiency of network inference and training.In terms of architecture,the hierarchical routing multi-core design is adopted,which supports routing multicast,partial sum extension,and inter-chip interconnection.This design improves the efficiency of neuron connections while ensuring the scalability and flexibility of the architecture.We also developed a hardware simulation model for this design,which integrates performance analysis tools.Based on the simulation model,the network computing mode,mapping method,architecture performance and application verification are studied.Finally,the temporalcoding SNN is functionally validated for training and inference based on the RRAM array test board.The above results demonstrate the potential of this design for low-power adaptive intelligent edge computing equipments from both theoretical and experimental perspectives.
Keywords/Search Tags:Neuromorphic Computing, Computing In Memory, Electrolyte-Gated Transistor, Memristor, Synaptic Plasticity, Spiking Neural Network Accelerator
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