Key Module Design And Prototype Verification For Digital Neuromorphic Computing

Neuromorphic computing becomes an art-of-edge domain with the help of excellent bio-plausibility and high energy efficiency of spiking Neuron Network(SNN).Several neuromorphic computing chips have been introduced to us these years.However almost these chips used one-dimensional neuron model,which can not perform biological details very well.meanwhile,few neuromorphic computing chips using two-dimensional neuron model also have been achieved.but in these designs,two-dimensional neuron model costs hardware resources highly and whole neuromorphic computing system has poor scalability.This paper studies on key modules of digital neuromorphic computing hardware:To deal with the problem that one-dimensional neuron model has poor bioplausibility,Fitzhugh-Nagumo(FHN)neuron model is used as basic operation unit in this design.FHN neuron model can simulate more patterns of biological pulse sequence than Leaky Integrate-and-Fire(LIF)neuron model and have simpler operation flow than Hodgkin-Huxley(HH)neuron model.Therefore,FHN model is more suitable for constructing an efficient SNN hardware with full biological details.To deal with the problem that two-dimensional neuron model has high cost of hardware resources,in this design,Mathematical function of the model is discretized by Euler method to replace differential operation with numerical iteration.Using function fitting by Hyperbolic Sine solves high-order terms with 0.5% fitting error.Using shift operation to replace multiplication leads to multiplier-free design.Using pipeline structure optimizes operation timing and rises clock frequency.To deal with the problem that existed neuromorphic computing systems have poor scalability,we have designed core module of the neuromorphic computing system.128 neurons and 128 stimulus current generator modules are integrated in a single core.The core module also includes two scheduling modules for neuron data synchronizing and data format conversion,one weight look-up table module for weight quantization which reduce 75% storage.As fundamental unit of whole system,core modules are organized by network-on-chip(No C)and it is easier to enlarge scale of system.At the same time,we design a parameter configuration network built with hierarchical bus architecture.full duplex 100 M speed UDP protocol is used for data exchange between host computer and our neuromorphic computing system hardware.With these methods,the interface of system is more compatible.Simulation test and FPGA prototype verification on FHN neuron module,core module and communication network module have been carried in this paper.According to the results,single neuron model occupied 1536 LUT and no multiplex DSP has been consumed.Core module and communication network module performs correctly with correct timing.