| Compared to the conventional electrical cables,the fiber/waveguide-based optical interconnects yield better results in channel bandwidth,energy loss,crosstalk,and electromagnetic interference（EMI）,which have been indispensable to accommodate the high-speed and high-capacity data interconnects.Furthermore,the silicon-based optoelectronic technology improves the speed of data transmission by utilized optical signal,which is leading a trend of the next optical interconnects’development for its inexpensive and high integration density.As a key building block of the optical communication system,the silicon-based optical receiver become a research hotspot naturally.In order to realize the problems of current researches on silicon-based optical receiver and meet the demand of 100 Gbps（10×10 Gbps,4×25 Gbps,100 Gbps PAM4）optical communication,such as the poor performance of silicon-based photo detector,the bandwidth drop of the cascaded single-stage amplifier,and the abuse of area-occupied inductors,this thesis has carried out the researches on the architectures of the hybrid/monolithic-integrated optical receiver in silicon,the differential photo detector（PD）in standard CMOS technology,the single-stage amplifier of the modified Cheery-Hooper,inductor-less bandwidth extension techniques and the bandwidth limit of the circuit for the transmission of several hundred Gbps.And the detailed research works are as follow:1.The 10 Gbps monolithic-integrated and differential optical receiver has been designed,fabricated,and measured.Based the research on the architectures of the monolithic optical receiver in silicon,the differential PD and optical receiver analog front-end circuit（RX＿AFE）were proposed and integrated in a single chip.Fabricated in TSMC 180 nm CMOS technology,the electro-optic measurements indicated that the proposed optical receiver exhibited a-3 d B bandwidth of 6.8 GHz,a transimpedance gain of 98 d BΩand a power consumption of 155 m W from the supplied voltage of 2.2V/9.7 V（RX＿AFE/PD）.And the sensibility of-3 d Bm@10-12 was reached when the 10Gbps 7-order pseudo-random binary sequence（PRBS7）was operated.2.The 25 Gbps hybrid-integrated optical receiver has been designed,fabricated,and measured.To address the bandwidth drop of the cascaded common-source amplifier,the inverter-based modified Cheery-Hooper amplifier was presented,which is used in the design of the transimpedance and limiting amplifier.Fabricated in SMIC 55 nm CMOS technology,the measurements indicated that the proposed optical receiver exhibited a-3 d B bandwidth of 21.7 GHz,a transimpedance gain of 73 d BΩand a power consumption of 56 m W from the supplied voltage of 1.2 V/.And the sensibility of 3 m Vp-p@10-12 was reached when the 25 Gbps 27-1 pseudo-random binary sequence（PRBS7）was operated.3.The two 100 Gbps optical receiver analog front-end circuit（RX＿AFE）has been separately designed,fabricated and measured.To address the channels’bandwidth pressure of 100 Gbps optical communication,the 4×25 Gbps not return to zero（NRZ）RX＿AFE and 100 Gbps pulse amplitude modulation 4（PAM4）RX＿AFE were proposed.As for 4×25 Gbps NRZ RX＿AFE,the inductor-less bandwidth extension techniques were brilliantly adopted in design of the transimpedance amplifier（TIA）and limiting amplifier（LA）,and small area-occupied 100 Gbps RX＿AFE was accomplished.Fabricated in SMIC 55nm CMOS technology,the measurements indicated that the chip exhibited a-3 d B bandwidth of 22.8 GHz,a transimpedance gain of 76 d BΩand a total power consumption of 226 m W from the supplied voltage of 1.2V.And the electronical sensibility of 2.5 m Vp-p@10-12 was reached when the 25 Gbps7-order pseudo-random binary sequence（PRBS7）was operated.In addition,the crosstalk between the adjacent channels was less than-22 d B in the-3 d B bandwidth.The 100 Gbps PAM4 RX＿AFE was mentioned,the AGC and emitter negative feedback were utilized to hold the constant output swing and improve the linearity.Fabricated in IHP 130nm Bi CMOS technology,the measurements indicated that the chip exhibited a-3 d B bandwidth of 35 GHz,a transimpedance gain of 58-72 d BΩand a constant output voltage of 440 m Vp-p from the supplied voltage of 3.3 V.And the ratio of level mismatch（RLM）was over 0.8 when the 64-Gbps PAM4 was operated. |
