| With the gradual popularization of 5G technology and high-speed Internet technology,the speed and bandwidth of backbone networks have been significantly improved.The maturity of communication technology provides a reliable guarantee for Io T development.The vision of Io T is to connect all device terminals and sensor nodes within sight into the network.Through the server and cloud data integration,the unified assessment and scheduling of the status of each node device are realized.LPWAN provides a low-cost,low-power,long-range communication standard for long-distance and low-data volume devices.The advantages of LPWAN in solving the low-cost communication of Io T have made it rapidly become a hot spot for academic and market attention,and the enthusiasm is gradually increasing in recent years.The low-power,long-range transceiver chip is the key physical foundation in LPWAN communication.It receives and decodes the wireless signals,analyzes the upper-level network scheduling requirements,and feeds the node information to the upper-level gateway.Transceiver chips suitable for LPWAN are power,cost,and transmission distance sensitive.Therefore lower cost,lower power consumption,and higher energy conversion efficiency are the development directions of wireless transceiver chips for LPWAN nodes.Many research works and products have demonstrated that wireless transceivers for LPWAN can be monolithically integrated based on existing CMOS technology.This is undoubtedly beneficial for the cost reduction and promotion of the use of such transceivers.This dissertation is dedicated to studying key technologies of low-power long-range CMOS wireless transceiver chips applied to LPWAN nodes.The improvement of the overall performance of the transceiver system depends on the innovation of the structure and the performance optimization of the basic circuit modules.The dissertation first analyzes the application characteristics of wireless transceivers adapted to LPWAN.The specific indicators of each module circuit are refined according to the overall link budget results,laying a good foundation for the modular design.Next,the receiver and transmitter links’ overall design and modular innovation are carried out separately for the index requirements.This dissertation studies LPWAN communication requirements,and a transceiver architecture suitable for LPWAN is designed.A receiver architecture without an analog filter is proposed.The asymmetric characteristics of LPWAN node signals are studied,and a transceiver architecture with the asymmetric receive-transmit link is proposed.The design difficulty and chip cost of the LPWAN transceiver are reduced.In terms of module design,the key modules of the low-power long-range transceiver,such as low-noise amplifier(LNA),low-power phase-locked loop(PLL),and power amplifier(PA),are theoretically studied and analyzed and circuit designed with cost and power consumption as constraints and long-range transmission as the goal.The following research results have been obtained.This dissertation investigates the structure and design method of the broadband low-noise amplifier(LNA)analyzes the structure of broadband-matched LNA and the advantages and disadvantages of each structure.The structures of noise cancellation LNAs and their respective advantages and disadvantages are summarized.By combining noise-cancellation and feedforward linear optimization techniques.A feedforward linearity optimization technique that can be used for LNAs is proposed.This technique breaks the constraint relationship between noise cancellation and linearity.It enables the LNA to meet the noise cancellation condition while improving the linearity without additional power consumption.Based on this,a linearity-optimized LNA is designed using a 65 nm CMOS process to meet the demand for low power and high linearity of LPWAN transceivers.The LNA has a 3 d B bandwidth of 100 MHz to 3.5 GHz,a maximum in-band gain of 17 d B,and an in-band input third-order cross-tuning point(IIP3)of 4～9.4 d Bm,with a noise figure of merit(NF)of only 2.09～3.2d B.In this dissertation,we studied the architecture and design method of a low-power phase-locked loop(PLL)and summarized a low-power PLL design method.Based on the consideration of chip area and power consumption,we chose a PLL based on ring oscillator and based on 180 nm CMOS process,a phase-locked loop circuit with adjustable frequency from 300 MHz to 500 MHz is designed.The phase noise is better than-110 d Bc/Hz@1MHz,while the average power consumption of the whole phase-locked loop operation is less than 3m W.In this dissertation,CMOS power amplifiers are investigated,and a Class F power amplifier is implemented for the needs of LPWAN transceivers.The designed power amplifier has a good power increase efficiency(PAE)of about 56%.The maximum output power operating in the frequency band of 300MHz～500MHz is 21 d Bm.Harmonic power is less than-40 d Bm.This study investigates the cascade problem of each key module.Through software simulation,layout planning,post-simulation analysis,and other steps,iterative simulation,the complete layout design of the overall receiver and transmitter architecture,which includes cascade processing,link planning,key alignment processing,high and low-frequency module isolation,pad and electrostatic protection design,etc.we completed the complete layout design of the receiver chip and transmitter chip,and the post-simulation of the full process corner was done.The transmitter part has been completed for the test.The receiver part is waiting for verification.In summary,this dissertation investigates the key CMOS technology for LPWAN.,and the module-level metrics are designed for the transceiver link in terms of power consumption and performance,starting from the receive channel and transmit channel,respectively.The power consumption and performance of the key modules of the transceiver are optimized.Although the research and design of this dissertation are for wireless transceivers under the LPWAN protocol,the link analysis methods,noise cancellation,linearity optimization,low power design,and other techniques mentioned in this dissertation are also applicable to the design of wireless transceivers. |
