Research On Reliability Of 4H-SiC Power MOSFETs

Silicon carbide（SiC）material has excellent properties such as wide band gap,high critical breakdown electric field,high electron saturation velocity and high thermal conductivity,which make SiC power devices very suitable for high-temperature,high-voltage,and high-power applications.As an important high-power control device in electronic power systems,SiC MOSFETs have great potential to replace the existing Si based IGBT devices in the blocking voltage range of 300-4500V due to their advantages of high switching frequency and low conduction loss.This significantly increases the switching speed and reduces switching losses of the whole system.However,there are still some reliability problems in SiC power MOSFETs:threshold voltage shift caused by traps near the 4H-SiC/SiO₂ interface,deterioration of electrical properties in the long-term operation caused by SiC material defects,and the avalanche failure during dynamic switching.And these problems become more prominent as chip area and on-resistance decrease.The reliability problems mentioned above greatly restrict the further improvement of commercial application of SiC MOSFETs.To solve the above problems,theoretical and experimental studies on static and dynamic reliability problems encountered by 4H-SiC power MOSFETs are carried out in this paper.The main research contents and innovative results are as follows:1)The reliability characterization method of SiC MOS structure devices is studied.For the interface traps,near-interface traps and oxide layer traps existing near the 4H-SiC/SiO₂interface,the corresponding characterization methods are proposed respectively.An F-N tunneling model is established to analyze the inherent mechanism of gate dielectric leakage,which provides theoretical support for the characterization of gate dielectric reliability.The key points of high temperature reverse bias and high temperature gate bias test are analyzed and discussed to provide guidance for characterizing the long-term reliability of SiC MOSFETs.The experimental scenarios,principles and characterization methods for single-pulse avalanche test are studied,which lays the foundation for the characterization of the dynamic reliability of SiC MOSFETs.2)The effects of nitrogen passivation conditions on the interfacial states,near interface electron and hole trap density,oxide layer electron and hole trap density are investigated.The effects of NO annealing time on the leakage characteristics and reliability of the gate dielectric of MOS capacitor samples are studied by gate leakage test and bias stress test.The results show that increasing NO annealing time increases the peak content of nitrogen at the4H-SiC/SiO₂ interface,which leads to the decrease of the interface and the near-interface electron trap density of n-type MOS capacitors,but it increases the near interface hole trap density of p-type MOS capacitors.Therefore,nitrogen passivation improves the forward stability of the threshold voltage of SiC MOSFETs but deteriorates its negative stability.It is precisely due to the reduction of electron traps and the increase of hole traps near the interface that the F-N tunneling point of n-type MOS capacitors is shifted to the left,while the F-N tunneling point of p-type MOS capacitors is shifted to the right.This reduces the forward gate bias range during device operation and expands the negative gate bias range during device turn-off.During the time-dependent bias stress test,as the oxide traps are continuously filled with charges,the gate leakage level of the MOS capacitor decreases,and the F-N tunneling point gradually advances.With the increase of nitrogen annealing time,the electron trap density of n-type MOS capacitors decreases,the filling rate of electron traps slows down,and the change rate of F-N tunneling point with stress time decreases;With the increase of nitrogen annealing time,the hole trap density of p-type MOS capacitors increases,the filling rate of hole trap becomes faster,and the change rate of F-N tunneling point with stress time increases.To further verify the effect of nitrogen annealing conditions on the interface properties,the mobility,interface-state density,and threshold voltage shift of the experimentally prepared SiC MOSFETs with different nitrogen annealing conditions are characterized.The results show that increasing the NO annealing temperature and increasing the annealing time can significantly improve the channel electron mobility,and the maximum field effect electron mobility increases by 80%.But it leads to the obvious negative shift of threshold voltage during the gate bias stress test.In the+25 V gate bias stress test for 500 s,the negative shift of the maximum threshold voltage increases by 56%.And the subsequent high-temperature gate bias test results show a trend consistent with this.Therefore,the selection of nitrogen annealing conditions needs to compromise from the channel mobility,the reduction of threshold voltage positive shift and the increase of negative shift.At the same time,it also needs to consider its influence on the positive and negative gate bias range of the device.3)The effects of SiC surface morphologic defects on device characteristics,long-term reliability and interface quality are investigated.By comparing the location information of SiC surface morphologic defects with the electrical characteristics and reliability test results of MOSFET devices,the correlation between morphologic defects and device failure modes is studied.The effects of triangular defects,epitaxial pits and carrot defects on the devices are compared using SiC MOSFET and MOS capacitor samples.In general,triangular defects have more fatal effects on device performance and yield than other morphological defects.The analysis results of defects on the characteristics and reliability of SiC MOSFET devices show that triangular defects can easily lead to serious degradation of the reverse leakage and gate leakage characteristics of SiC MOSFET devices,resulting in device failure,and the failure rate is as high as 93%.The impact of epitaxial pits is the second,and the failure rate is 47%.The high temperature gate bias and high temperature reverse bias tests are carried out on the devices containing epitaxial pit defects without degradation.It is found that compared with the devices without morphologic defects,the threshold voltage shift of the devices with epitaxial pit defects is greater and the increase of gate leakage is more obvious,indicating that the presence of morphologic defects can adversely affect the device reliability in long-term operation.Furthermore,the effects of surface morphologic defects on the trap density near the 4H-SiC/SiO₂ interface and the gate dielectric integrity of the SiC MOS capacitors are investigated by the same technical method.The analysis results of defects on the interface characteristics of SiC MOS capacitors show that compared with devices without morphologic defects,carrot defects and triangular defects increase the density of interfacial traps,near-interface traps and oxide traps,and the effect of carrot defects is more obvious.This makes the threshold voltage of the device deviate from the design value,and the threshold stability becomes worse.It also leads to an increase in the leakage of the gate dielectric,and the gate leakage characteristic curves appear obvious discretization.The uneven phenomenon of SiC epitaxial surface caused by morphologic defects is simulated by TCAD tool.The simulation results of gate leakage show that the electric field concentration inside the gate dielectric caused by morphologic defects is the main reason for the degradation of the gate dielectric.4)The single pulse avalanche failure mechanism of 4H-SiC power MOSFETs is studied.An accurate electro-thermal simulation model is constructed for the simulation of avalanche process,which includes the thermal capacitance and thermal resistance of the passivation and encapsulation layers at the top and bottom of the device.The model fully considers the influence of thermal conductivity control mode and heat capacity control mode on the internal heat transfer process of the chip.The good agreement between the test results and the simulation results verifies the effectiveness of this model.According to the single-pulse avalanche test results of SiC MOSFET and the UIS thermal process simulation analysis of half-cell and multi-cell,the intrinsic mechanism of device avalanche failure is clarified.The decapping inspection of the failed devices reveals that the direct cause of failure is the formation of hot spots rather than the melting of the surface aluminum electrodes.The UIS simulation results of the half-cell show that the increase of the internal junction temperature of the device during the avalanche process can lead to the activation of parasitic BJTs and eventually the device failure.The simulation results of multi-cell devices show that due to the slight difference in parameter distribution between cells,the BJT of a cell will be activated first,quickly form the concentration of current and temperature,and finally lead to the formation of hot spots.The more the number of cells,the more obvious this concentration phenomenon is.Considering that the device area size of SiC MOSFET is smaller than that of Si-based devices with the same current level,and its power density is also higher,there are higher requirements for the uniformity of parameter distribution between cells within the SiC MOSFETs.In addition,the effects of ambient temperature,load inductance,off-state gate voltage and channel length on the avalanche capability are analyzed by simulation.The results show that increasing the ambient temperature can reduce the built-in potential of the parasitic BJT,resulting in a lower avalanche tolerance.Increasing the load inductance can change the heat transfer path inside the chip,change the heat transfer process from heat capacity control mode to heat conduction control mode,and improve the avalanche robustness of the device.A lower off-state negative gate voltage can improve the avalanche robustness,but deteriorate the negative stability of the threshold voltage.Shortening the channel reduces on-resistance,but it also degrades avalanche robustness.Therefore,trade-offs need to be considered in the device design.5)The effect of active region doping profile on device avalanche robustness is investigated.Various retrograde P-well doping profiles are designed,and the effects of different widths of lightly doping region and concentrations of heavily doping region of P-wells on the on-resistance,blocking voltage and avalanche robustness of the device are analyzed by analytical calculation and TCAD simulation.And the optimized P-well doping profile is given.The analytical and simulation results show that reducing the thickness of the lightly doped region in the retrograde P-well region can suppress the activation of parasitic BJT,making the avalanche robustness enhanced as the thickness of the lightly doped region decreases,but this increases the on-resistance.However,the change of the thickness of the P-well lightly doped region has no obvious effect on the blocking ability.Considering the control of the threshold voltage,the thickness of the lightly doped region of the P well should not be less than that of the N+region.Increasing the concentration of the heavily doping region of the retrograde P-well can enhance the device avalanche robustness,but it also increases the electric field concentration at the bottom corner of the P-well,resulting in the degradation of the blocking characteristics.The degradation of blocking characteristics can be alleviated by arranging a low-doped region at the bottom of the retrograde P-well,and finally a low-high-low three-region P-well doping profile is proposed.Compared with the traditional uniform P-well doping,the three-region P-well doping can reduce the on-resistance of the device from 15 mΩ·cm² to 12 mΩ·cm² and improve the avalanche tolerance from 22 J/cm² to 36 J/cm² under the condition of meeting the blocking voltage requirements（above 1600 V）.The contradiction between improving avalanche robustness and device static characteristic degradation can be effectively alleviated.Finally,for short-channel devices,the effects of different ion implantation concentrations in the JFET region on the static electrical characteristics and avalanche tolerance of the device are analyzed by simulation.By increasing the doping concentration of the JFET region,the conduction characteristics of the device can be significantly improved,but the avalanche robustness and static blocking characteristics are degraded.Using the retrograde doping profile of the JFET region can effectively improve the avalanche tolerance with an increase of 16.85%while maintaining the blocking characteristics unchanged.The on-resistance only increased by6.19%.