Electrical Characteristics And Reliability Of MOSFET Capacitors With Ultra-thin Oxides

In the present study, we investigated I-V and C-V characteristics of MOSFET capacitors with different oxide thickness fabricated by a standard dual-gate process. It was found that direct tunneling instead of Forler-Nordheim tunneling is the dominant conduction mechanism of gate leakage for the oxides with thickness less than 30 A. Additionally, interface defects contribute an additional component to the high gate leakage of ultra-thin oxides. As far as the characterization of interface defect density is concerned, the traditional methods of CV and charge pumping are not so suitable to the ultra-thin oxides. It is very necessary to develop a new method to accurately characterize the interface defect density of ultra-thin gate oxides.By comparing the gate leakage current before and after electrical stress, we investigated the stress induced leakage current (SILC) characteristic and its conduction mechanism. The method to characterize the stress induced interface defects was developed using the SILC of ultra-thin oxides. It was found that the SILC of ultra-thin oxides strongly depends on the sense voltage, especially at the low sense voltage (denoted as LV-SILC). The LV-SELC is due to interface trap assisted tunneling (ITAT) mechanism and is linearly related to interface trap density (D_it). Therefore, it was used to probe the generation of stress induced interface defects. The generation of interface defects is a nonlinear process. As the stress time increases, interface trap generation rate decreases. When D_it, reaches a critical value, D_it,crit, oxide quasi-breakdown takes place. It is interface traps that play a key role in the oxide breakdown. Generation of interface traps as a function of stress time was used to...