Font Size: a A A

Analysis And Characterization Of Conductance Characteristics Of 4H-SiC MOS Capacitor

Posted on:2023-11-21Degree:MasterType:Thesis
Country:ChinaCandidate:Y W CaiFull Text:PDF
GTID:2558307097475484Subject:Electronic Science and Technology
Abstract/Summary:
Silicon carbide(Si C)is one of the most representative third-generation semiconductor materials.Si C has the characteristics of high voltage resistance,high frequency resistance and high temperature,so it has received the focus of the semiconductor industry.However,at present,Si C devices are not widely used in various power electronic systems,mainly because of various defects in Si C devices,resulting in poor performance and low reliability of Si C devices.There are many methods for testing and characterizing defects in Si C devices.Among them,the conductance method can test the information of defects under the condition of fixed gate voltage and temperature,so as to ensure that the energy band structure of the system is basically unchanged during the whole testing process.It is easier to obtain information on defects at specific energy levels,rather than the overall effect of defects at a certain width of energy levels.Therefore,this paper hopes to study and explain the electrical phenomena caused by defects by means of the low-temperature conductometric method,in order to provide theoretical reference for the analysis and evaluation of electrical test results of Si C devices and provide theoretical guidance for the direction of process improvement.In this paper,the low temperature conductance method was used to test the structure of a silicon dioxide/silicon carbide(Si O2/Si C)MOS capacitor,and three types of conductance peaks are extracted:broad,narrow,and broad and narrow.According to the previous research results and reasonable speculation:the narrow conductance peak may be caused by carriers tunneling to near interface defects or by bulk doping impurities.Since there is sufficient evidence to prove that the broad conductance peak is caused by the interface states,this paper focuses on establishing the quantitative model for the narrow conductance peak from the energy band perspective and deriving the corresponding theoretical conductance curve,and in the existing interface states theory the quantitative model of the broad conductance peak is described in detail below for the subsequent analysis and comparison of defects.Finally,by fitting the theoretical conductance curves and the experimental conductance curves and extracting the defect information,it is found that:(1)The carriers tunneling into the near-interface defect can only occur in the depletion region where the surface potential is almost 0e V,when the surface potential is small,the tunneling distance is negative,so this model cannot reasonably explain the formation of narrow conductance peaks;(2)The quantification model of bulk doping impurities can well explain the reasons for the appearance of narrow conductance peaks.The theoretical conductance curves of the model fits well with the experimental narrow conductance curves,and the extracted dopant concentration decreases as it moves away from the Si O2/Si C interface,and the SIMS test proves the correctness of the extraction result;(3)The quantitative model of the interface state fits well with the broad conductance peak,and the information of the interface state can be extracted more accurately.Since the broad and narrow conductance peaks appear near the flatband,the role of bulk doping impurities,interface states and near-interface defects may exist at this position.In addition,the effects of near-interface defects on C-V characteristics were simulated by Sentaurus TCAD software to further explore the mechanism.In summary,by studying the conductance peaks of different shapes,reasonable attributions and explanations have been given to them from the microscopic mechanism.The characterization of defects in this paper is no longer limited to defects such as interface states and near-interface defects,but focuses on the process also affecting the doping in the semiconductor.In a way,the low-temperature conductance method is a non-destructive method for doping impurity concentration.However,due to the constraints of the test conditions,this subject cannot test the narrow conductance peaks that appear at lower frequencies under the low temperature environment and at higher frequencies under the high temperature environment.Therefore,the bulk doping model can be further improved and perfected in this direction in the future.
Keywords/Search Tags:SiC MOS, conductance method, doping impurities, interface states, near interface traps
Related items