Research On Key Technologies Of Wafer-Scale Monolithic Pixel Sensors For The ALICE ITS Upgrade

A Large Ion Collider Experiment(ALICE)is a dedicated heavy-ion detector at the Large Hadron Collider(LHC).Its innermost sub-detector,the Inner Tracking System(ITS2),is a vertex detector equipped with seven concentric layers of Monolithic Active Pixel Sensors(MAPS).During the preparation and installation of ITS2,the ALICE collaboration proposed a novel vertex detector,called ITS3,consisting of three cylindrical layers of curved wafer-scale stitched sensors.This innovative detector features an unprecedented material budget of 0.05%X0 per layer,only one-seventh that of ITS2 inner layers.It will replace the ITS2 inner barrel(three innermost layers)in LHC long shutdown 3.This dissertation presents the design and development of the wafer-scale stitched sensor for the ITS3 detector.All activities are based on the TowerJazz Panasonic Semiconductor 65 nm Imaging Sensor CMOS(TPSCo 65nm ISC)process that offers stitching technology and fabrication on wafers of 300 mm diameter,allowing the realization of the entire ITS3 half-cylinder as a single chip.The radiation hardness of this process has been verified using customized Transistor Test Structures(TTS).Measurements show a radiation tolerance of 1.2 V core transistors up to 100 Mrad.The radiation effects and degradation mechanisms are similar to other 65nm CMOS processes,strongly dependent on transistor size.Quantitative characterization of radiation effects is reported,which offers a guideline for designers in this process,particularly for radiation-hardened applications.The MAPS performance depends on many parameters,such as process modification,pixel size,sensor geometry,and reverse bias voltage.To explore the process and sensor characteristics,a series of small-scale monolithic active pixel sensor prototypes,Analog Pixel Test Structures(APTS),have been manufactured.Each APTS chip contains a 4 × 4 pixel matrix with high-speed analog outputs directly buffered to pads for off-chip real-time observation of all pixels in parallel.Different chips include pixels with various process modifications,pixel pitches(10 μm-25 μm),geometries,and reverse biasing schemes.Laboratory and beam tests demonstrate that the process modification significantly accelerates charge collection and reduces charge sharing.In addition,large pixels with the process modification perform nicely with no evident degradation.Another small-scale prototype,the Digital Pixel Test Structure(DPTS),features a 32 × 32 binary pixel matrix at 15 μm pitch.It employs an asynchronous event-driven readout architecture with GHz range time-encoded digital signals,including Time-Over-Threshold information.This prototype allows early verification of the novel sensor geometry,front-end,and key aspects of the TPSCo 65nm ISC process.It is proven fully functional and efficient in test beam and a full efficiency is retained after irradiation up to 1015 1 MeV neq/cm~2 at room temperature.The sensor achieves a time resolution of 7 ns and a spatial resolution of 4 μm at 100 nA pixel current consumption.Increasing reverse bias voltage helps to reduce the sensor capacitance and hence increases the signal-to-noise ratio.However,it also significantly affects the operating point through the body effect on NMOS transistors within the pixel matrix.This effect appears to be underestimated in the simulation for significant reverse substrate bias outside of the standard supply voltage,and this is studied by correlating back to measurements of individual transistors.Based on the silicon-proven sensor structure and front-end in DPTS,the MOnolithic Stitched Sensor chip(MOSS)is a stitched prototype with an area of 1.4 × 26 cm~2,designed to explore the feasibility of stitched particle detectors with satisfactory yield.It consists of one left endcap,ten repeated sensor units,and one right endcap.Every repeated sensor unit is divided into the top and bottom half units.This dissertation will focus on the design of MOSS mainly from three correlating aspects:yield,pixel design,and power consumption.Concerning the yield,every half unit has an individual power domain to maximize operating granularity,and the reliability of cross-domain signaling is ensured by design.For the pixel design,similar in-pixel circuits are realized in 18 μm and 22.5 μm pitches for the bottom and top half units,respectively,but with more conservative layout rules in the latter.This method not only allows the exploration of the yield dependence on layout densities and spacing but also provides two candidates for the full-scale stitched sensor.Regarding power consumption,the advantage of the large pitch matrix is obvious.However,the most critical block is rather the data transmission over a long distance.Therefore,a detailed analysis is carried out to find an optimal trade-off between its power consumption and time performance for our application.