Study On High-Speed And Low-power Data Transmission Circuits Of CMOS Pixel Sensors

Development of particle detectors brings in an era of the CMOS pixel sensor(CPS),the most critical performance parameter of which is resolution.Resolution includes spatial resolution and time resolution.Spatial resolution is highly restricted by featxire sizes of CMOS technology,whereas time resolution is more dependent on circuit design and closely involved with clock frequency and data transmission rates.Under the project of the development of particle detectors between Dalian University of Technology and University of Strasbourg in France,this dissertation focuses on improvement of data rates of the transmission circuits of CPS based on a 0.18 ?m CMOS technology,while maintaining the merits of CPs,such as high spatial resolution and low power consumption.The main contributions of this dissertation are listed as follows.1)According to requirements of a high data transmission rate(?1 Gb/s)and low power budget for the vertex detector in the upgrade of a large ion collider experiment(ALICE)in Europe,a low-voltage differential signaling(LVDS)circuit was designed.A Iatch-up circuit composed of a current comparator was adopted and power-off mode was added during the circuit design,achieving high-speed signal transmission with low power consumption.Based on this,the LVDS circuits were integrated into the input/output cells,resulting in a smaller dead zone of particle detectors.The measurement results of the taped-out chip show that the circuit achieves goals of a data rate of 1.2 Gb/s and a power consumption of 19.6 mW,and thus is adopted as the data trarnsmission circuit in the CPS for the upgrade of ALICE.2)In the upgrade of the ALICE,transmission distance of signals for the vertex detector is approximately 30 centimeters of traces on a printed circuit board plus 4-5 meters of cables.According to this characteristic of short-distance transmission,a scheme of data transmission implemented using low-power reduced swing differential signaling(RSDS)circuits was proposed.During the design of the RSDS receiver,power consumption was reduced by methods of narrowing the common-mode voltage range,improving the hysteresis-generating circuit and so on,while maintaining high-speed transmission data rates.Measurement results of the chip show that the circuits consume only a power of 19.1 mW at a data rate of 2 Gb/s.The RSDS circuits consume up to 17%less power than the LVDS circuit at a data rate of 1 Gb/s.3)According to requirements of the compressed baryonic matter(CBM)experiment in Gennany,further improvement of data transmission rates has highest priority,whereas the budget of power consumption can be properly relaxed.Therefore,a LVDS driver capable of higher data transmission rate was designed by the use of source parallel impedance matching,at the cost of reasonable increment of power consumption.For the clock input signals,it achieves a data rate of 2.5 Gb/s.The total power consumption of the high-speed LVDS driver and the LVDS/RSDS receiver is only 27.2 mW at this data rate.4)To solve the problem of synchronization between clock and data for one CPS chip,and that among multiple CPS chips,a wide tuning range phase-locked loop(PLL)circuit multiplying its input frequency by a factor of 16 was designed,taking operation frequencies of several vertex detectors into consideration.The difficulty in the design of this PLL is to achieve low jitter over the entire range of tuning frequencies.To overcome the difficulty,an adaptive-bandwidth architecture was adopted and an appropriate bandwidth was designed firstly,resulting in reduction of contributions of the voltage-controlled oscillator to PLL jitter over the entire tuning range.Secondly,a self-biased circuit was introduced to decrease the contributions of noise from power supply and ground.Thirdly,topology of the charge pump was modified to diminish its noise.Finally,a second-order loop filter was used to suppress high-frequency components of jitter.Measurement results show that this PLL circuit implements the frequency multiplication of by a factor of 16.Furthermore,the total jitter is less than 0.2 unit interval in the tuning range from 80 MHz to 800 MHz.The designed PLL circuit not only solves the synchronization problems,but also extends the frequency range of the clock of CPS chips,providing necessary for the application of CPS chips to vertex detectors with precise time resolution.