Research Of High Event Rate And High Resolution TDC ASIC Prototype For Silicon Pixel Detectors

Silicon pixel detectors are often integrated as track detectors to the position closest to the beam in accelerator particle physics experiments because of their good position resolution.With the gradual development of pixel detectors,it has also been applied in other fields,such as the field of X-ray imaging.To satisfy the requirements of different application scenarios,the pixel detector does not only need to have the capabilities of position resolution with high precision,but also needs to have capabilities of energy and time measurement with high precision.The measurement of the deposited energy of the pixel detector can use TOT(Time-Over-Threshold)technology to convert the energy measurement into a pulse width measurement.Therefore,the ability to obtain high-precision time information is an important direction for the optimization of the detector.This dissertation focuses on improving the time resolution capability of silicon pixel detectors.Based on the investigation of typical methods about time interval measurement and existing means to acquire the time information in silicon pixel detectors,a design scheme of a high-precision TDC(Time-to-Digital Converter)ASIC(Application Specific Integrated Circuit)prototype circuit which can handle the special output signal of front-end readout electronics in pixel detectors,which is characterized by that the shortest time interval between adjacent pulses is 500 ps.and there are up to 11 continuous pulses in a short period of time,has been proposed.The TDC will be integrated at the end of the pixel column as a core circuit.The TDC adopts the method of combining coarse and fine measurement,among which the coarse time measurement adopts the direct counting method,and the fine time measurement is implemented by combining the TAC(Time-to-Amplitude Converter)with ADC(Analog-to-Digital Converter).The prototype circuit has been completed based on 130 nm process and also been simulated.The simulation results indicate that the circuit has the capability processing up to 11 consecutive events in which the time interval between adjacent events is as small as 500 ps,while the bin size of TDC is about 2 ps,the DNL(Differential Non-Linearity)is better than 3 ps,and the time measurement precision is better than 8 ps rms.For the systematic test of TDC ASIC in the future,this paper also designed a multi-channel TDC verification circuit system based on FPGA(Field Programmable Gate Array)and built a test platform.Then,a test and verification of a 16-channel FPGA TDC has been completed on this platform,which make preparation for the next step of testing.