Design And Characterization Of A MAPS For The CEPC Vertex Detector

Chinese scientists proposed building a next-generation Circular Electron Positron Collider(CEPC)and later upgraded it into a Super Proton Proton Collider(SPPC)to study the Higgs boson and look for new physics at the energy frontier.One of the challenges faced by the CEPC is to construct a vertex detector(the innermost subdetector system)capable of providing excellent position resolution,fast readout,and low material budget.To accurately measure the properties of the Higgs boson,the spatial resolution of the vertex detector must be less than 5 μm.At present,the pixel sensors developed by the largest ATLAS and CMS experiments on the Large Hadron Collider(LHC)in Switzerland have spatial resolutions of 10 μm or more.Although the ALPIDE pixel sensor in the ALICE upgrade of the heavy-ion experiment and the MIMOSA pixel sensor in the STAR experiment can reach a position resolution of 5μm,the readout speed of these chips is not enough(10 kHz to 100 kHz).The bunch crossing of 40 MHz and a dead time of less than 500 ns,needed for the CEPC,cannot be achieved.Thus,it is necessary to design an advanced dedicated pixel sensor according to the physical requirements of CEPC.A MAPS prototype,TaichuPix,with non-zero compression data-driven and a column-drain readout architecture,has been implemented to provide a fast readout and high spatial resolution for the CEPC vertex detector.This series of chips includes a sensing cell,in-matrix front-end electronics,peripheral readout logic,and highspeed serial data interface modules.It is targeted to develop and verify a prototype for the baseline vertex detector of CEPC.The main content and innovation aspects of the dissertation are presented below:This dissertation implements a fast readout,non-zero compression data-driven prototype chip TaichuPix for the CEPC vertex detector.The chip improves the readout speed in the array from both analog and digital parts.In the analog part,by enhancing the gain of the analog front-end pre-amplifier,the peaking time is optimized from the conventional few microseconds to less than 400 ns,ensuring the high-speed readout of subsequent digital readout circuitry.The matrix readout speed improves rapidly in the digital readout part by a token ring priority encoder and non-zero compression data-driven approach.The readout time of this prototype is around 50 times shorter than the JadePix2 solution under a full-scale matrix with the same hit rate.The FEI3 readout chip architecture of the ATLAS pixel detector is improved to adapt it to a 25×25μm2 pixel size.It combines high spatial resolution and fast readout.The FEI3 chip array uses data-driven readout and token priority to transfer data to the end of the column.However,the pixel size is 400×50 μm2,and the complete readout logic cannot be implemented in a 25×25 μm2 area.Therefore,a column-drain-based readout architecture is proposed.The timestamp is not stored inside the pixels but at the end of the column,and the ROM that stores the hit information is changed to a direct address encoding MOS transistor matrix,and a double-column scheme is used to share the readout bus.Thus,the area of the readout logic circuit is reduced to 13.7×25 μm2.A two-level FIFO architecture is proposed to solve the high data rate readout of a 1024×512 matrix.The peripheral readout logic needs to consider the pixel hit rate and an acceptable dead time.The most stringent condition given by the CEPC CDR is to meet the readout frequency of 120 pixels per microsecond per chip in W boson events.Therefore,this dissertation studies a dedicated high data rate digital peripheral readout.Each double-column is read out in parallel.Every hit pixel is encoded with a 32-bit word,and the hit information is buffered in a column FIFO with a depth of 12 at a clock frequency of 40 MHz.Then it is sent to the chip-level FIFO with a 160 MHz output clock to achieve the data readout frequency of 120 pixel/μs.The TaichuPix1 test platform was designed based on the ZC706 SoC FPGA.The radioactive source 90Sr was used to verify the full functionality of the chip.The charge deposited from the β particle ionization is amplified by the analog front-end circuit and converted into a voltage signal.Then the position information can be digitalized successfully under the 40 MHz operating clock.At the same time,an external trigger experiment setup with a scintillator was used to verify the function of the trigger mode,and the average cluster size was 2.6.Compared with the ALPIDE of a 29.24×26.88μm2 pixel size,the smaller pixel size of TaichuPix1 is expected to achieve a spatial resolution of less than 5 μm.