| In recent years,as the market’s requirements for product quality have increased,and technologies such as sensors and industrial buses have continued to advance,the amount of data to be processed for automatic visual inspection of products has become larger and larger,and the processing speed requirements for visual inspection methods have also increased.The research of visual inspection methods usually involves the development of image feature extraction algorithms.Feature extraction is a key preprocessing step to achieve tasks such as object detection,defect recognition,shape measurement,and 3D reconstruction.As the most time-consuming link in visual inspection,feature extraction greatly affects the inspection efficiency of the system.This thesis studies the FPGA acceleration technology for the key feature extraction algorithm that limits the speed in the visual inspection system.The research hopes to solve the problems of low parallelism,inefficiency of processing architecture,sacrifice of accuracy and poor scalability in existing acceleration schemes,so as to achieve highspeed processing of visual inspection tasks.The main work completed and innovations are as follows:(1)The research status of visual inspection acceleration technology is systematically investigated from system architecture,software and hardware,and the problems in the existing acceleration schemes are summarized.Then the basic design methods in FPGA acceleration technology are studied.In order to meet the high throughput requirements of visual inspection feature extraction,an acceleration module interface design scheme with data stream interface as the main one and on-chip memory interface and external memory interface as supplemented is proposed.And using visual programming tools,a general image acquisition,storage and display FPGA program for acceleration algorithm realization and verification is designed.(2)For the high-speed detection of surface defects,a multi-level parallel FPGA structure design method is proposed.For periodic texture feature filtering,in order to solve the boundary effect problem of the traditional one-dimensional Fourier reconstruction algorithm,an improved algorithm based on sub-pixel period and complete period truncation is proposed,which can effectively eliminate the defect detection surface texture.On this basis,the overall structure of FPGA acceleration with task parallel and pixel parallel,resampling structure based on look-up table with pixel parallel,and onedimensional Fourier reconstruction algorithm bit width connection structure with separate processing of high and low data bits and sign bit extension are designed.Combining the above methods,the surface scanning detection speed of the liquid crystal panel is increased by more than 3 times,which meets the system’s online processing requirements,and significantly improves the accuracy of defect detection.(3)Aiming at the problem that the fixed-point bit width of data in FPGA hardware implementation significantly affects the accuracy of laser stripe center extraction,a data bit width optimization method for mixed dynamic and static analysis is proposed.Based on the analysis of the existing problems in the current FPGA structure of Hessian matrix calculation,a separate symmetric,row-column convolution multiplexing structure with large template size is designed.Then,using bit width constraint conditions and data range analysis methods,and based on the indicators of maximum position deviation,average position deviation and number of error points,the data bit width of each intermediate variable of the Steger algorithm is jointly optimized,thus obtaining a fixed-point accuracy that is superior to the regular bit width design and other existing methods.Pixel parallel and full pipeline design also make our scheme meet the real-time data processing needs of Gigabit network cameras.(4)In order to improve the efficiency of phase and point cloud computing in the phase-shifting fringe projection profilometry system,a heterogeneous processing acceleration scheme of FPGA and CPU is proposed.For the wrapped phase calculation module,an octant phase mapping structure based on lookup table is designed,which can greatly improve the fixed-point accuracy of the phase calculation;for the phase unwrapping module,a frame-level pipeline structure based on iteration is designed,which can effectively reduce the delay;and for multi-camera system,we present a scalable solution that can be adjusted according to the degree of pixel parallelism.Combining the above methods,higher measurement accuracy and architecture efficiency are achieved,and the above scheme can support high-speed 3D point cloud computing at 50.86 frames per second for two cameras. |
