WCDMA/GSM Dual-mode Multi-band RF Receiver Research And Design

The presented thesis is about design of a multi-mode multi-band reconfigurable receiver for 2G/3G cellular applications, implemented in CMOS process.The receiver adopts a multi-channel architecture to support multiple frequency bands, which is consisted of three independent RF channels optimized for WCDMA Band I (IMT 2100), GSM High-band (1800/1900) and GSM Low-band (850/900), respectively. Zero-IF Architecture is used for WCDMA while Digital Low-IF is used for GSM. Analog baseband, ADC and digital front-end (DFE) are shared between two modes through register configuration. The receiver is integrated in a single-chip transceiver with PLL, TX, ADC/DAC and DFE.A new link budget analysis method based on SNR calculation is proposed. Receiver module specifications targeting SAW-less WCDMA has been analyzed, including gain, noise figure, linearity, filter selectivity, ADC dynamic range and anti-blocking performance. System simulations have been performed to verify problems like intermodulation or cross-modulation products from modulated signals, which are difficult to calculate in theory. Noise coupling mechanism concerned in full-chip TRX integration has been presented, as well as corresponding floorplaning and isolation technique.Circuit level design techniques of critical modules in receiver chain are presented. Parasitic aware source degeneration LNA design and optimization method have been demostrated. Design aspects of current mode passive mixer have been thoroughly studied. Based on its impedance transformation characteristics, an integrated design method considering LNA, passive mixer and TIA as a whole block has been proposed, which can simultaneously optimize gain, noise and linearity of the receiver front-end. The mixer is driven by 25% duty cycle LO for better performance, this also eliminates I/Q crosstalk in a quadrature down-converter. DC offset and second order intermodulation have been analyzed. Digital assisted calibration circuits are also intensively used in the presented receiver.Two versions of receiver chips have been implemented in 0.13um RFCMOS process based on the above discussions. Targeted specification is met. Impedance matching in all required frequency bands is realized, receiver maximum gain above 74dB, noise figure of 5dB, in-band IIP3 of -6dBm and calibrated IIP2 beyond +65dBm have been measured. Receiver sensitivity level is -109 dBm from BER measurement. Total receiver power consumption is 120mW in WCDMA mode and 70mW in GSM mode, supply voltage is 1.5V. Total chip area of fully integrated TRX is 5.1x5.5mm2.