| With Moore`s law fading, presence of billions of transistors on a single chip, and diminishing performance from uniprocessor architectures, multicore chips are emerging as the prevailing architecture in both application-specific and general-purpose markets. As the core count increases, the need for a scalable on-chip communication fabric that can deliver high bandwidth continues to gain importance, leading recently to multicore chips interconnected with on-chip networks. Networks-on-Chip (NoC) is widely regarded as a promising approach for addressing communication challenges affiliated with Chip Multi-Processors (CMPs) in the face of further increases in integration density. However, throughput, energy efficiency and routing algorithms become more challenging in NoC design.;To address throughput and energy efficiency, we evaluate Virtual-channel Allocation (VA), Switch Allocation (SA) in terms of matching quality, delay, area and power using RTL implementation. Based on the results of this study, we propose centralized priority management allocation (CPMA) router architecture to improve matching quality, delay, area, and energy efficiency. By coordinating arbiters' priority in the first allocation stage, CPMA increases the matching quality. The centralized priority unit can also reduce each arbiter's design complexity. The improvement of matching quality and reduction of design complexity make the router more energy efficient with less area consumption.;The dissertation next focuses on NoC routing algorithms. A parameter that can indicate the traffic congestion is needed for the routing algorithm to select the best path. In this dissertation, we propose predictive passing time as a parameter for the routing algorithm. Instead of indicating the traffic congestion, predictive passing time reflects the time it will take the message to go through the path. This parameter makes the routing algorithm more accurate in choosing among different paths. In NoC, a broken router can isolate a functional processing element (PE) from other nodes, severely restricting the performance of the system. To solve this issue, we present a new routing algorithm that can transmit the message to the isolated PE even when the router is broken.;The approaches used here in Network on Chips can be adapted to Chip Multiprocessor and multicore systems. |
