| The development and manufacturing of microprocessor integrated circuits (ICs) is becoming an ever more difficult task with decreasing IC feature sizes. Ever since the introduction of silicon-based ICs, it has been predicted that the feature sizes of these ICs would continue to decrease, and therefore lead to more transistors being packed onto a single die. Although a natural consequence of this increased transistor density has been the reduced cost of IC-based systems, new design methods had to be introduced to make effective use of the increased IC density. Along with the design of microprocessor ICs, the manufacturing of ICs has also seen new challenges as a result of transistor-dense dies. During the manufacturing process, each transistor must be thoroughly tested to ensure its correct functionality, which becomes more difficult as more transistors are packed on a die.;In past, the power density of ICs was small enough that it was an afterthought of microprocessor design, but as ICs have become more transistor-dense, this is no longer the case, since increased IC power density can lead to device failure, device damage, or devices not suitable for their desired application (e.g., mobile computing). During test, these problems are especially problematic since the power density during test is higher than during normal device operation, and the violation of power constraints during test can lead to higher IC manufacturing costs. Along with increased power density, increased device temperatures have also become a problem for IC design with recent technologies, as high device temperature can damage a device. High temperature is especially problematic during test, since the environment of test is less temperature-friendly than normal device operation.;The goal of this work is to address power and temperature constraints in a manufacturing test environment. To reduce the testing time under power and temperature, this work will make use of technology previously used in advanced microprocessors (dynamic voltage and frequency scaling). This work will also present a scheduling formulation that incorporates many different constraints to allow the scheduling of tests under many different environments. |
