THE DESIGN AND PERFORMANCE OF A PARALLEL COMPUTER ARCHITECTURE FOR SIMULATION

The objective of this research is to develop an efficient parallel digital computer architecture for the numerical solution of ordinary differential equations with initial value conditions. Such a digital computer would be useful as a replacement of analog or hybrid computers in high speed real time simulation. Existing digital computers do not operate at speeds fast enough to match the performance but require problem scaling and programming difficulties.; This research consists of five specific phases. First, the computer architecture is formulated by an analysis of the parallelism inherent in the block diagram structure of simulation problems. Second, a performance model is developed for this architecture. Third, the performance model is used to select numerical integration and function evaluation techniques which maintain the desired accuracy levels and computational speed. Fourth, several benchmark problems are implemented on an experimental prototype. Fifth, measurements for the performance model are taken from the experimental prototype and used for comparison with existing analog and digital systems.; The results of this research define a new architecture for the solution of systems of ordinary differential equations. A number of asynchronous processors, each with local program and data memories, is connected to a parallel interconnection network controlled by a sequencer.; An experimental prototype capable of supporting 32 processors has been designed and built. Two types of processor modules have been developed. These are a general purpose floating point processor using the Intel 8086/87, and a custom designed, high-speed, microprogrammed, fixed point processor. Based on benchmark studies, the prototype machine using fixed point processor modules is capable of solving, in real time, differential equations of sixty-fourth order or less with an 1100 hertz bandwidth at 0.1% error. The floating point processor has a real time solution bandwidth of 30 hertz.; The performance of this architecture using fixed point processor modules is equivalent to that of analog/hybrid computers and exceeds that of current high performance scientific digital computers. Scaling of variables is required, similar to analog/hybrid computers, but programming is less difficult.