Modeling Interface Engineered Phase-Change Memory Cel

Due to its outstanding scalability, phase change memory is regarded as a promising memory technology to enhance non-volatile storage in ultra-small feature size. However high power consumption remains the biggest obstacle on its way to market. Although interface engineering has been proved experimentally to be an effective way for power reduction, the mechanism is not completely understood hence the effect has not been included to any model for circuit simulation.;Investigation on current reduction mechanism by interfacial layer insertion is conducted based on cell structure and interfacial material property. Comparison between prediction and experimental data give insights to the most possible current reduction mechanism, which is further verified by cross check of resistance and threshold voltage change brought by additional layer. The selected mechanism provides solid base for further model development on interfacial effects.;Prior to incorporating the effect of interface engineering, a general model for phase change memory cell with generic structure is proposed. The proposed general model is able to reveal of detail dimension of phase change region, which is the most crucial factor for storage status of the cell. The model is proved to be universal regardless of the cell geometry and the shape of the phase change region. Based on the active geometry model, resistance is calculated with conformal mapping method and its 3-D extension, and the switching process is described in the form of a circuit model which is capable to reproduce the newly discovered voltage oscillation phenomenon. Additionally the effect of interface engineering is modeled according to the mechanism selected previously. The models include the effect of interface engineering on static resistance, active dimension, programming current and threshold voltage, which are able to construct the complete static and dynamic characteristics of PCM cell.