Free-space direct-detection optical communication with semiconductor laser transmitters and avalanche photodiode photodetectors

This dissertation consists of a theoretical and experimental study of the performance limits of a free-space direct detection optical communication system using a semiconductor laser diode as the optical transmitter and a silicon avalanche photodiode (APD) as the receiver photodetector. Optical systems using these components are under extensive consideration as replacements for microwave satellite communication links. Due to the peak and average optical power output constraints inherent in semiconductor laser diodes, optical pulse position modulation (PPM) was chosen as the most appropriate signal format.; An experimental system was constructed that used an AlGaAs ({dollar}lambda{dollar} = 833nm) semiconductor laser diode transmitter and a silicon avalanche photodiode photodetector. The system used Q = 4 PPM signaling at a source data rate of 25 {dollar}times{dollar} 10{dollar}sp6{dollar} bits/second. A nearly exact computational procedure was developed to compute receiver bit error rate (BER) without using the Gaussian approximation. A transition detector slot clock recovery system using a phase lock loop (PLL) was developed and implemented. A novel word clock recovery system was also developed in which a phase lock loop was used to track the random occurrence of back-to-back PPM pulse pairs on the received data stream.; It was found that the results of the nearly exact computational procedure agreed well with measurements of receiver performance. Use of the widely accepted Gaussian model for the APD was shown to underestimate the optimal value of average APD gain and substantially overestimate the receiver BER when the average number of detected background noise photons was less than one per PPM slot time. The receiver achieved a BER of 10{dollar}sp{lcub}-6{rcub}{dollar} at 55 average detected signal photons per bit. This is best receiver sensitivity yet reported for a direct detection system of this type. The transition detector slot clock recovery scheme was simple to implement and yet caused no measurable penalty in receiver sensitivity when the PLL noise bandwidth was less than 10{dollar}sp{lcub}-4{rcub}{dollar} of the slot clock frequency ({dollar}<{dollar}1% output phase jitter). The new word clock recovery scheme was shown to perform well too. The entire timing recovery subsystem could start acquire and maintain receiver synchronization at as low as 15 detected signal photons per bit.