| Embedded random access memories (RAMs) are increasingly being tested using built-in self-test (BIST) circuits, because an embedded RAM's signals are not accessible through input/output pins. Given current trends, the size of embedded RAMs will eventually grow so large that yield considerations will require the use of redundant lines for repair. Then, BIST circuits will need to not only detect faults, but also locate faults for repair. The designs of two different BISD circuits (one with, and the other without, self-repair capability) appropriate for repairable, embedded, (single-metal and single-polysilicon layered) CMOS static RAMs, are presented. The implementation of a BISD circuit--with self-repair--requires 15% extra area in a 16K SRAM, and 5% extra area in a 64K SRAM. The BISD circuit contains a reduced-instruction-set processor, which executes diagnosis algorithms stored in a read-only memory, and which uses some extra lines to access the memory. The new algorithms employ "hybrid serial/parallel" operations to access the memory when external repair is available, or "modular" operations to access it when self-repair is required. |
