| As the sizes of VLSI devices increase rapidly, generating high quality manufacturing tests which can be applied at native speeds is becoming a serious problem. This dissertation presents a novel method for hierarchical functional test generation for deep submicron designs. This method targets one embedded module at a time and uses commercial test generation tools to derive tests for faults within the module. A transformed module, which embodies functional constraints described using virtual logic, is used for the module level test generation. The transformed module patterns are then translated back to the processor level. The technique is, however, useful only if the virtual logic can be generated automatically. An automatic functional constraint extraction algorithm and a procedure to build the transformed module is developed. The tool, FALCON, is used to extract the functional constraints of a given embedded module from a high level or gate level description.; It is shown that, using the proposed technique, test generation complexity is reduced by several orders of magnitude. Applying the technique to benchmark processor designs, we are able to generate test patterns of the same quality as the tests generated with a complete access to the module. When the same tool is used, the proposed technique required several orders of magnitude less time than when using a conventional flat view of the circuit. In addition, the conventional approach did not achieve the same fault coverage as the hierarchical one.; Traditionally gate level testability analysis is used to analyze testability bottlenecks in a design. In order to make the design decisions effective, it is desirable to perform testability analysis using high level description of a design. We have introduced an analysis procedure to identify testability bottlenecks very early in the design. To improve the identified bottlenecks, a Design For Testability (DFT) technique is proposed. Results indicate that the DFT technique reduces the test generation complexity and can be used with the proposed hierarchical test generation technique.; The module abstraction techniques developed in this dissertation can have applications beyond test generation. The technique was applied to hierarchical fault simulation, and results are reported on the modules from the benchmark processors. |
