| As general purpose processors become increasingly complex, the task of testing them also becomes more difficult. Because of the tremendous verification space presented by a processor, numerous test cases are needed to sufficiently exercise the processor. An automatic test generation system is a software tool embedded with the knowledge of the processor instruction set and behavior. It generates tests which can run on either a simulation model or the actual processor chip. The goals of the system are to provide a large bandwidth of test cases and, in doing so, cover as much of the verification space as possible. A large bandwidth of tests is achieved by automating the test generation task. The functional coverage of these tests is maximized by employing pseudo-random generation of interacting instruction sequences. Because test execution is still the primary method of testing processors at the chip level, automatic test generation systems are heavily relied upon in industry. However, existing automatic test generation systems do not significantly cover the virtual memory operations.; For several generations of general purpose processors, virtual memory support has been a necessary feature. But it usually remains largely untested until the processor is robust enough to boot up an operating system. Even then the processor may still contain many errors related to its virtual memory operations. In order to test virtual memory operations earlier in the design cycle and provide more coverage, automatic test generation systems must overcome some problems. This dissertation presents these problems and describes the design and implementation of an automatic test generation system that thoroughly covers the virtual memory operations of a pipelined superscalar commercial processor. The problems and solutions are general and apply to all general purpose processors, including Reduced Instruction Set Computers (RISC's), although the system was designed to test an X86 processor. |
