| This research work studies the geometrical effect on electromigration, which is a failure mechanism due to momentum exchange of moving electrons and host lattice, in Very Large Scale Integrated (VLSI) circuits. In a typical VLSI circuit, there exist millions of transistors connected by a system of multilevel metal interconnect. As the VLSI circuit continually shrinks in size for better functional performance, the embedded transistors increase in number leading to more levels of metal stacked vertically. Via or plug, the vertical connection between two levels of metal conductor, becomes important and poses as the reliability bottleneck of the whole metal interconnect system. Reliability requirement if met by the via, the bottleneck, guarantees lifetime satisfaction for the whole interconnect system.; Although the via is believed to degrade interconnect reliability performance, the weakest geometrical configuration in an interconnect system is yet to be studied and identified. This is because the via and the metal conductor are electrically connected and thus affect each other's reliability performance intimately and uniquely. Therefore, a subtle change in geometry of the structure either in the metal conductor or in the via plug itself can cause a significant change in electromigration performance of the structure.; In this research work, several test structures are designed and fabricated to study the impact of device geometry on its electromigration performance. These devices take into consideration the impact of electron flow directions, via current density, and stress gradient-induced diffusion phenomenon, namely the reservoir effect on device electromigration performance. From experimental data, a physical model and an empirical equation are built to predict the lifetime of the weakest geometrical configuration that involves a via in a metal interconnect system. |
