| In this research, we use FPGA technology to design a reconfigurable switch that provides architectural support for high performance computing. The proposed design can be dynamically configured to support a variety of interconnection topologies and different communication requirements. The change in configuration improves the performance, network throughput, reliability, and cost effectiveness of a high performance computing system, built using the proposed reconfigurable switch. Furthermore, the design uses parallel message routing and distributed control strategy to achieve the required high performance.; We use the switch to build a high-speed dynamically reconfigurable multi-link ring network and show how to embed hypercube topologies on that network. The same approach can be generalized to other interconnection topologies. The proposed switch design supports both circuit and packet switching communication. In addition, it uses virtual channels flow control and wormhole routing to improve the network performance.; Performance analysis of the multi-link ring network has also been investigated. In that analysis. two approaches have been used to develop an analytical model that analyzes the virtual channel access delay. The first approach uses the M/M/n and M/D/n queuing models (infinite state Markov models), while the second approach uses a finite state Markov model to analyze that delay. Analytical results show that less number of virtual channels per link provide better performance at low loads. On the other hand, more number of virtual channels provide better performance at high loads. In addition, simulation, using the OPNET tool, has been performed to verify the analytical results and to investigate the impact of some communication parameters on network performance. Simulation results indicate that the second approach is more accurate in analyzing the behavior of the packet transfer time in the proposed network. Other experimental results that measure the packet transfer time (latency) for different numbers of virtual channels, network sizes, packet sizes, and routing schemes have also been reported.; We also explore how the switch reconfiguration can be utilized to emulate FDDI, ATM, and DQDB networking technologies. In addition, we discuss how to use the switch to build a High Performance Distributed Computing system which is flexible to support a variety of communication requirements, or construct a dynamically reconfigurable multicomputer system based on a 2-d torus interconnection. |
