| Testing of VLSI designs must usually be done under strict design constraints, and must fit within a designated area and delay budget. Conventional design-for-testability approaches often involve adding logic to improve the controllability or observability of difficult-to-test portions of the design. The area and delay associated with this added logic is of great concern to designers, particularly in performance-critical applications like digital signal processing (DSP). Often, the addition of even a single added layer of logic for testing purposes can significantly impair performance. This work focuses on the testability problems encountered in applying built-in self-test (BIST) techniques to such designs.; Issues addressed include logical redundancy, random-pattern test-resistant structures, circuit/test-generator incompatibilities, and test quality. By addressing these issues early in the design process, a design's testability can be significantly improved, with a corresponding decrease in the product's defect level. With a behavioral model of testability guiding design, we find that large data-paths can be restructured so as to reduce test length by two orders of magnitude. Alternatively, for a fixed test length, a factor of eight reduction in the number of untested faults is demonstrated.; This research finds that high fault coverage (in the 99% range) may not be sufficient to guarantee product quality in some cases due to systematic testing failures stemming from basic test-generator/circuit incompatibilities. However, these risks can be addressed through the use of efficient redundancy identification, accurate fault simulation, mixed test generation schemes, and analytical techniques that identify test failures and rank test quality from a functional perspective. These techniques are developed and demonstrated on large digital filter designs. |
