Image Coding And Vlsi Design Based On Wavelet Transform

With the development of multimedia technique, image compression plays a more important role in the storage and transfer of mass image data. The image coding method based on wavelet transform has many advantages, such as high compression ratio, precision control of bit rate, excellent reconstructed image quality and being capable of encoding and decoding gradually. Consequently,fast wavelet image coding algorithms with high performance and their hardware implementation become the research focus in image compression domain currently.Aiming to very large scale integration (VLSI) circuits design of the image compression algorithms, the research carried out in this dissertation mainly are the efficient and fast algorithms of two-dimension discrete wavelet transform (DWT) and wavelet coefficients'coding techniques, and some excellent VLSI architectures of them.Taking into account of the shortcut of computation complexity of DWT, a 9/7 wavelet filter with simple coefficients is adopted, and it is also realized in filter bank of convolution whose critical path is shorter than lift scheme for one dimension DWT. The fixed point model of wavelet transform is simulated by software tool to ensure high quality of reconstructed image, and then the bit width of wavelet coefficients is ascertained. An effective direct architecture of 2-D DWT is introduced in which two data buffers FIFO are used to achieve multi-level 2-D DWT in time-sharing and pipeline way. The architecture is designed in hardware description language, and its implementation is simulated, synthesized and then downloaded to the FPGA board for verification.The coding of wavelet coefficients in real-time is also explored in this paper. Classical coding algorithms including Embedded Zerotree Wavelet (EZW) and Set Partitioning in Hierarchical Trees (SPIHT) are analyzed and simulations are done to prove their coding performance. An improved No List SPIHT algorithm is presented considering the hardware implementation requirements, which increases the coding speed and reduces the memory cells, and its quality of reconstructed image is nearly equal to that of SPIHT algorithm.Finally,the VLSI circuits design of zero-tree coding algorithm is implemented through the high level synthesis tool. To satisfy different image application needs, the encoder supports eight choices of compression from 128 times to nearly distortion-free. The results of simulation and test show that the circuit can work at a high speed and its performance can meet the real time desire of image compression.