A deep submicron drain-current and charge model for MOS transistors

A unified short-channel Metal-oxide-semiconductor (S-CMOS) transistor model has been developed for design and simulation of deep-submicron mixed-signal very large-scale integration (VLSI) circuits for high-speed computing, high-frequency communication, and multimedia applications. Unified expressions for drain current, conductances, terminal charge, and capacitances are derived with the assistance of three smooth functions including hyperbola, exponential interpolation, and sigmoid functions, which provide excellent transitions between different regions of operation. A compact set of 35 parameters is used to characterize transistor behavior. Effects of non-uniform substrate doping, drain-induced-barrier-lowering, narrow-channel and reverse short-channel are included in the threshold voltage expression. Mobility reduction due to lateral and vertical electrical fields is modeled by including the second-order term to provide high accuracy for deep-submicron transistors. The charge/capacitance model uses an accurate formulation for back-gate degradation coefficient to model the channel charge density. The unified expressions of charge densities are derived which are valid for all operation regions including the accumulation region. Different channel-charge partitioning schemes, including 40/60, 0/100, and 50/50, are provided to have better usage of the model in various applications. Parameter extraction of S-CMOS model is based on physical meaning of each model parameter, and is implemented by using MATLAB program. Both the local determination and global optimization strategies are combined to increase the extraction accuracy and reduce computation time. The S-CMOS model is implemented in a modified version of the popular SPICE-3f3 circuit simulator from University of California, Berkeley. Simulation results of mixed-signal circuits including domino logic gate, folded-cascode operational amplifier, analog comparator, wide-range Gilbert multiplier, and DRAM circuit are presented. Comparison of simulated results and measured data of transistors demonstrate the accuracy of the S-CMOS model and its strong capability in the deep-submicron technologies. In the appendix, research work on modeling MOS transistors for use up to 10 GHz is described with careful comparison of measured and simulation results.