| Diagnostic ultrasound has become a popular imaging modality because it is safe, noninvasive, relatively inexpensive, easy to use, and capable of real-time imaging. In order to meet the high computation and throughput requirements, ultrasound machines have been designed using algorithm-specific fixed-function hardware with limited reprogrammability. As a result, improvements to the various ultrasound algorithms and additions of new ultrasound applications have been quite expensive, requiring redesigns ranging from hardware chips and boards up to the complete machine. On the other hand, a fully programmable ultrasound machine could be reprogrammed to quickly adapt to new tasks and offer advantages, such as reducing costs and the time-to-market of new ideas.; Despite these advantages, an embedded programmable multiprocessor system capable of meeting all the processing requirements, of a modern ultrasound machine has not yet emerged. Limitations of previous programmable approaches include insufficient compute power, inadequate data flow bandwidth or topology, and algorithms not optimized for the architecture. This study has addressed these issues by developing not only an architecture capable of handling the computation and data flow requirements, but also designing efficient ultrasound algorithms, tightly integrated with the architecture, and demonstrating the requirements being met through a unique simulation method.; First, we designed a low-cost, high performance multi-mediaprocessor architecture, capable of meeting the demanding processing requirements of current hardwired ultrasound machines. Second, we efficiently mapped the ultrasound algorithms, including B-mode processing, color-flow processing, scan conversion, and raster/image processing, to the multi-mediaprocessor architecture, emphasizing not only efficient subword computation, but data flow as well. In the process, we developed a methodology for mapping algorithms to mediaprocessors, along with several unique ultrasound algorithm implementations. Third, to demonstrate this multiprocessor architecture and algorithms meet the processing and data flow requirements, we developed a multiprocessor simulation environment, combining the accuracy of a cycle-accurate processor simulator, with a board-level VHDL (VHSIC Hardware Description Language) simulator. Due to the large scale of the multiprocessor system simulation, several methods were developed to reduce component complexity and reduce the address trace file size, in order to make the simulation size and time reasonable while still preserving the accuracy of the simulation. |
