Theory, practice, and fundamental performance limits of high-speed data conversion using continuous-time delta-sigma modulators

We consider the design of high-speed continuous-time delta-sigma modulators for analog-to-digital conversion. Many of the nonidealities that affect performance in discrete-time modulators do likewise in continuous-time modulators, yet there are three additional important considerations unique to continuous-time modulators. The first, excess loop delay, is the time delay between the quantizer clock and the output of the feedback, which affects stability and dynamic range; its effect can be reduced by employing return-to-zero-style DACs and feedback coefficient tuning. The second, clock jitter, whitens the output spectrum in the quantization noise notch and lowers SNR; a carefully-designed VCO will alleviate its effects for all but very wideband or high-resolution modulators. The third, quantizer metastability, also whitens the output spectrum and lowers SNR; it is essential to use a three half-latch quantizer over a simple master/slave design to provide extra regeneration, and even then it is best not to clock faster than about 5% of maximum transistor switching speed. A design procedure is given for band pass modulators whose intended application is conversion of analog signals at one quarter of the sampling frequency, and a fabricated 4GHz modulator for 1GHz signal conversion is simulated, tested, and redesigned to improve its performance from 6 bits to 10 bits. Finally, the appropriateness of high-speed continuous-time delta-sigma modulation is considered for various applications.