Computer-aided testing of switching and interconnect resources of FPGAs

The boundary scan standard as proposed by the IEEE Standards Board in Std 1149.1 has made possible the efficient testing of computer boards. This standard regulates the testing of chips as well as the interconnect between them. As boards may have hundreds of thousands nets in the interconnect, the problem of wiring diagnosis is important and acute. Fault detection in a system environment necessitates a different fault model and approach than the traditional interconnect testing scenario as usually encountered within a board. New fault detection and built-in-self-test strategies under new fault models are required for efficient testing of interconnects. FPGAs are a revolutionary new type of user programmable integrated circuits that provide fast, inexpensive access to customized VLSI. The interconnect resources of FPGAs are important for programming flexibility and high performance of many commercially available FPGAs. For FPGAs, faults (such as shorts and opens) are also likely to appear in the interconnect as it occupies an area larger than the logic resources. The high density and complexity of FPGAs require that testing and diagnosis must be efficiently implemented to diagnose the occurrence of faults due to either short or open or stuck-at in the interconnect resources.; The dissertation addresses the following issues related to interconnect testing: (1) improving adaptive strategies for maximal diagnosis of interconnects; (2) developing strategies for interconnect testing in a tristate environment; (3) designing BIST structures for interconnect testing; (4) developing strategies for testing of FPGA programmable interconnects.; We disprove a previous adaptive algorithm by a counterexample. Two improved adaptive algorithms are developed for reducing the total test length. The problem of interconnect testing in a tristate environment is discussed and a minimal detection set is proposed. New BIST structures for board level interconnect testing are proposed which combine some of the advantages of previous designs while introducing novel features which result in both low hardware overhead and a shorter test length. For testing of programmable interconnects in FPGAs, a new general approach is developed which is based on a bottom-up process and deals with both the switch block and the array through the execution of novel algorithms.