Circuits, Architectures, and CAD for Low-Power FPGAs

Field Programmable Gate Arrays (FPGAs) are becoming an ever more prominent platform for the implementation of digital systems. In contrast to traditional processors that map computations onto a series of predefined instructions, an FPGA maps a computation onto a custom tailored digital circuit, thus yielding performance benefits. FPGAs can also provide cost and time-to-market benefits compared to Application Specific Integrated Circuits (ASICs). However, these advantages do not come for free as FPGAs typically have higher power consumption than the aforementioned platforms. FPGA power consumption is specifically of great concern presently given the growing demand for compute power in power constrained environments such as in mobile devices and data centres. To that end, in this thesis we explore circuit and architectural techniques to reduce power dissipated in FPGAs, and present the necessary CAD tools to implement our proposed power optimization schemes.;First, we present a technique to reduce the dynamic power dissipation that arises because of glitches. For this technique we designed a programmable glitch filter which we propose to augment a conventional FPGA; the proposed circuit can be configured to eliminate glitches for a range of different pulse-widths. Our second power reduction technique is motivated by observing that there exists an abundance of unused routing conductors in FPGAs. We show that by tri-stating these unused routing conductors we can reduce the effective wire capacitance seen by adjacent conductors, thereby reducing dynamic power. Moreover, we show how tri-stated wires also results in reduced routing leakage. The third power reduction technique also seeks to leverage unused routing conductors; in this case we employ the unused routing conductors as charge reservoirs to enable a charge recycling technique to reduce dynamic power. Finally, this thesis presents a technique to aggressively reduce leakage power dissipated in the routing network of an FPGA by tri-stating both used and unused routing buffers; the used routing buffers in this case are temporarily activated when they are needed -- i.e. when they are in the process of transmitting data. Ensuring that all circuits are effectively shut-off at all other times allows us to reduce leakage power.