| The ever increasing complexity of the modern processor, combined with the advanced technologies used to implement it, has lead to two major bottlenecks in the processor development: verifying the design correctness and testing the manufactured chip for realistic defects. This research explores related techniques to address these two problems, and reports results and practical experiences of applying these techniques to processor designs from industry.; Simulation is the primary means of design validation in industry today. Generating functional validation tests for a modern processor design is usually a laborious, at-hoc and open-ended task. Clearly new techniques are needed to make it more systematic, automated and efficient. This work provides test generation techniques at three different levels, working in a synergetic fashion. First, an efficient automatic test generator is introduced, that produces instruction set architecture (ISA) tests to check all basic functionalities. Second, methodologies to validate performance enhancing architectural features are described. Algorithms exploiting the on-chip timer to test superscalar mechanisms, and a detailed case study of functional validation of a VLIW media microarchitectural validation. The technique identifies the control states from a microprocessor model in hardware description language automatically, and generates the path coverage task set. The finite state machine (FSM) transition tour is translated to system-level operations, which are concretized into assembly instructions. The FSM transition tour is also used in measuring the control behavior coverage of the existing verification suite.; These techniques for functional validation are extended to generating effective tests for manufacturing defects. While test generation and tester costs are beginning to dominate product costs, the available test techniques are only applicable to small modules, are limited in their capabilities, and generally have an adverse impact on performance. We develop a new approach which exploits the inherent processing power of the chips by utilizing the functional modules and architecture-level behavior to implement self-tests with comprehensive fault coverage. The generated assembly-level tests can be applied in a built-in self-test fashion. Experimental results on microprocessors show that validation test generation methods, combined with our native mode signature compression technique, produce high quality at-speed manufacturing self-test. |
